Semiconductor Packaging
GlobalFoundries Qualifies SLATE Wafer-to-Wafer Bonding on 9SW RF-SOI Platform
GlobalFoundries announced the production readiness of its SLATE wafer-to-wafer bonding technology on the 9SW radio-frequency silicon-on-insulator (RF-SOI) platform for advanced 3D integration in radio frequency applications. The technology is manufactured at GF’s 300mm facility in Si
3 min read
SEMICON West 2026 Returns to San Francisco October 13-15
SEMI announced that SEMICON West 2026 will take place October 13-15 at the Moscone Center in San Francisco. The event returns to the Bay Area after last year’s event in Phoenix. Registration is now open, with early-bird rates available until June 26. The semiconductor industry is expected t
3 min read
Manz Asia Delivers World's First 310mm × 310mm Panel-Level Packaging ECD Production System for AI and HPC Applications
Manz Asia has delivered the world's first 310mm × 310mm panel-level packaging (PLP) Electrochemical Deposition (ECD) mass production system to a customer production line. The system is part of the Omni x-series covering 310mm, 510mm, and 700mm platforms. The ECD platform supports bot
4 min read
San Jose Based Co-packaged Optics Expert Ayar Labs Appoints Sejal Patel Daswani as Chief People and Operations Officer
Ayar Labs announced the appointment of Sejal Patel Daswani as Chief People and Operations Officer. The position is newly created. In the role, Daswani will oversee the company’s people strategy and operations as Ayar Labs continues to expand globally and advance its technology to meet hyper
4 min read
Elon Musk Announces TeraFab Project: Joint SpaceX, xAI and Tesla Initiative Targets Terawatt-Scale AI Compute
Elon Musk has unveiled the TeraFab, described as the most epic chip-building exercise in history and a project that will “take things to the next level” by orders of magnitude. The initiative is a collaborative effort between SpaceX, xAI and Tesla to deliver one terawatt of compute pe
5 min read
Keysight Launches 3D Interconnect Designer for Chiplet and 3DIC Package Designs
Keysight Technologies, introduced 3D Interconnect Designer, a new tool added to its Electronic Design Automation (EDA) portfolio. The solution targets the complexity involved in designing 3D interconnects for chiplet-based and 3DIC advanced packages in AI infrastructure and data center appl
3 min read
Lam Research Unveils VECTOR TEOS 3D to Tackle 3D Chip Packaging Challenges for AI and HPC
Lam Research introduced the VECTOR TEOS 3D, a deposition tool designed for advanced packaging of chips used in artificial intelligence (AI) and high-performance computing (HPC). The tool addresses challenges in 3D stacking and high-density heterogeneous integration by providing ultra-thick,
2 min read
Advanced Packaging Market to Hit $79.4B by 2030, Driven by AI and Telecom Growth
Yole Group’s new "Status of the Advanced Packaging Industry 2025" report revealed that the advanced packaging market reached $46 billion in 2024, a 19% year-on-year increase following a 2023 downturn. The market is projected to grow to $79.4 billion by 2030, with a 9.5% CAGR from 2024 to 20
3 min read
Global semiconductor equipment billings rise 21% to $32.05 billion in Q1 2025, SEMI reports
On June 5, 2025, SEMI announced in its Worldwide Semiconductor Equipment Market Statistics (WWSEMS) Report that global semiconductor equipment billings reached $32.05 billion in the first quarter of 2025, a 21% increase year-over-year. The report noted a 5% quarter-over-quarter decline, consisten
2 min read
Analysis of the cleanroom market in India for semiconductor manufacturing
India’s accelerated push to develop a robust semiconductor manufacturing ecosystem is driving significant growth in the cleanroom market for semiconductor fabrication and research laboratories. This growth aligns closely with the expansion of the semiconductor industry. Additionally, precis
8 min read
Cleanroom in semiconductor manufacturing: Basic essential of a chip fab
When manufacturing semiconductor devices with features as small as 2 nanometers, even a speck of nearly invisible dust, approximately 1 micron in size, adhering to the wafer can render the device defective, leading to significant losses due to rejected wafers. To ensure high-quality production,
16 min read
Asahi Kasei introduces TA series sunfort dry film photoresist for advanced semiconductor packaging
Asahi Kasei has launched the TA Series of Sunfort dry film photoresist, designed for advanced semiconductor packaging used in AI servers, automotive, and IoT applications. The product targets the growing market for next-generation chip packaging within Asahi Kasei’s Material sector. It offe
2 min read
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