Design Guide
Thermal Interface Materials at the Edge of Their Envelope: What AI Chip Power Densities Are Exposing About TIM Qualification
By Dr. Pradyumna Gupta, Founder & Chief Scientist, Infinita Lab | Founder & CEO, Infinita Materials When an AI accelerator die dissipates 700 watts across a surface smaller than a playing card, with a thermal management chain holding that system
13 min read
Building in the Open: A Designer's Guide to Open Source Hardware
In 1817, a German inventor named Karl von Drais built a strange two-wheeled wooden contraption to get across the grounds of a royal garden faster. He called it a draisine. It had no pedals, no gears, no rubber you pushed it along with your feet like a scooter. It wasn't a great bicycle. I
11 min read
UC San Diego develops fingertip patch to monitor levodopa for Parkinson's
Engineers and neuroscientists at UC San Diego have developed a soft, wearable patch worn on the fingertip that continuously tracks how much Parkinson's medication is in a patient's system by analyzing their sweat, without needing a battery to run. The patch monitors
4 min read
UCLA Engineers Integrate Terahertz Systems onto Single Semiconductor Chip
UCLA researchers have developed a method to integrate terahertz optoelectronic functions onto one semiconductor chip, addressing longstanding challenges with bulky systems. Terahertz waves occupy the electromagnetic spectrum between infrared light and microwaves. They hold potential for ul
4 min read
Cadence Expands Collaboration with HPE on Digital Twin Platform for AI Data Center Modernization
Cadence has announced an expansion of its collaboration with HPE to accelerate digital twin-driven data center modernization for next-generation AI and high-performance computing (HPC) infrastructure. The collaboration integrates the Cadence Reality Digital Twin Platform, which virtualizes data c
4 min read
onsemi Launches GaNEXUS Gallium Nitride Power Portfolio with 40V to 650V FETs
onsemi has announced the launch of its GaNEXUS gallium nitride (GaN) power portfolio. The initial devices, now sampling, include GaNEXUS FETs across voltage ranges from 40V to 650V and 650V GaNEXUS Smart GaN FETs with integrated protection features. The portfolio targets applications in AI
3 min read
Should You Build Your Own AI-Assisted Silicon IP and EDA Tools? A Brutally Honest Analysis
The question lands on the desk of every engineering VP at a growing fabless firm, usually after a painful licensing renewal: Do we keep paying ARM and Synopsys indefinitely, or do we build our own stack? It is not a hypothetical anymore. India's Saankhya
13 min read
EMI Reduction in Automotive Power Devices: Design Strategies for Compliance, Safety, and Performance
EMI Reduction in Automotive Power Devices: Design Strategies for Compliance, Safety, and Performance by Giusy Gambino, Yasmin Abigail Chiarenza, and Sebastiano GrassoSTMicroelectronics, Cat
25 min read
Toshiba Develops Trench-Gate SiC MOSFET Technology for Lower On-Resistance and Enhanced Short-Circuit Robustness
Toshiba Electronic Devices & Storage Corporation has developed a technology for trench-gate silicon carbide (SiC) MOSFETs that reduces on-resistance while improving short-circuit robustness. The technology optimizes the bottom p-well structure formed under the trench and the design of the jun
2 min read
Why Aliro device makers are ready to unlock truly connected access control
The full release of Aliro 1.0 by the Connectivity Standards Alliance signals that the new industry standard for secure & interoperable access control is ready to offer a convenient alternative to proprietary solutions
8 min read
Fujitsu Launches Application Transform Powered by Kozuchi Generative AI Service for Legacy Source Code Analysis and Design Document Generation
Fujitsu announced the launch of Fujitsu Application Transform powered by Fujitsu Kozuchi, a generative AI service that analyzes source code and automatically generates design documents. The service reduces design document generation time by approximately 97%. It will be offere as a SaaS in Japan
3 min read
Copper Interconnects at the Breaking Point: Why They Are Failing in Sub-3 nm AI Chips
As artificial intelligence (AI) accelerators push toward 2 nm and below, the industry’s decades-long reliance on copper (Cu) interconnects in the back-end-of-line (BEOL) is facing fundamental physical limits. Gate-All-Around (GAA) nanosheet transistors—adopted by TSMC (N2), Intel (18A
6 min read
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