EDA
VeriSilicon Launches CPP2000 Camera Post-Processing IP for Embodied Robotics and Mobile Vision Applications
VeriSilicon announced the CPP2000 Camera Post-Processing (CPP) IP, which expands its Image Signal Processing (ISP) solutions with advanced post-processing capabilities. The CPP2000 is designed to improve image quality and visual perception for moving-camera systems in robotics, drone
3 min read
Synopsys Releases First Multiphysics Fusion Solutions for Chip Design
Synopsys, announced the availability of its first Multiphysics Fusion solutions for customer deployment. The solutions integrate golden signoff multiphysics analysis into timing signoff, design closure, multi-die, and analog workflows. They enable SPICE-accurate multiphysics timing analysis with
4 min read
How GeniSys is Fueling India’s Semiconductor Dreams
In an interactive talk hosted by Srinivasa Reddy N, Editor of EEHerald, executives from GeniSys GmbH shared insights into the company’s software solutions for advanced semiconductor manufacturing and their relevance to India’s expanding ecosystem of design centers and upcoming fabrica
5 min read
Si2 Releases Public AI for EDA Ontology Repository for Agentic System Development
The Silicon Integration Initiative (Si2) AI/ML Schema/Ontology Working Group has announced the public release of its AI for EDA Ontology Repository. The repository supplies the semiconductor design community with an ontology and associated use cases to support experimentation with EDA agentic sys
3 min read
DVCon U.S. 2027 Opens Call for Technical Submissions, Deadline September 7, 2026
The Design and Verifica
6 min read
Should You Build Your Own AI-Assisted Silicon IP and EDA Tools? A Brutally Honest Analysis
The question lands on the desk of every engineering VP at a growing fabless firm, usually after a painful licensing renewal: Do we keep paying ARM and Synopsys indefinitely, or do we build our own stack? It is not a hypothetical anymore. India's Saankhya
13 min read
Cadence Launches Level-5 Autonomous ChipStack AI Super Agent for Chip Design at Computex 2026
Cadence announced at Computex 2026 the industry’s first fully autonomous virtual agentic AI design engineer, extending its ChipStack AI Super Agent framework to Level-5 autonomy. The solution is built on Cadence’s AI-driven electronic design automation (EDA) portfolio using NVIDIA Nem
4 min read
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