Imec presented a 7-bit, 175GS/s analog-to-digital converter (ADC) at the IEEE International Solid-State Circuits Conference (ISSCC) 2026. The ADC, implemented in 5nm FinFET technology, features a core area of 250 x 250 µm² and a conversion energy of 2.2 pJ per sample. It achieves one of the highest sampling speeds reported while maintaining a compact size and low energy use.
The design addresses demands for higher throughput in AI- and cloud-driven data centers, particularly in optical communication networks and wireline interconnects, where high sampling rates beyond 100GS/s typically increase component size, interconnect lengths, parasitics, and energy consumption. The ADC builds on imec's 2024 ISSCC demonstration of a massively time-interleaved slope-ADC architecture, which was at least twice as compact as conventional designs with high power efficiency.
Two patented techniques enable performance at ultra-high speeds:
A linearization method shapes the slope signal to correct distortions.
Switched input buffers feed the 2,048-channel time-interleaved array, reducing electrical load and preserving signal integrity for wide bandwidth.
Peter Ossieur, portfolio director at imec, stated that the ADC provides a solution for digital-intensive wireline interconnects where area and power are critical constraints. Imec is developing a follow-on design in 3nm technology and exploring 14-angstrom nodes for future high-performance wireline data converters.
Ossieur noted that imec's work focuses on high-speed integrated circuits for communication, particularly optical transceivers and building blocks for increasing wireline data rates. The ADC advances beyond traditional SAR-based architectures at ultra-high speeds. Imec invites partners, including fabless companies in wireline connectivity, to join its ADC and DAC research programs, with options for licensing the IP portfolio.
The results were presented in the “Pipeline and Ultra-High-Speed Data Converters” session (Session 11) on February 17 at 10:05 PST. The presentation is titled "A Compact 7b 175GS/s Linearized Time-Interleaved Slope ADC with Switched Input Buffers" by Ewout Martens.
Imec is exhibiting at ISSCC 2026 booth #8 to discuss collaboration and licensing opportunities.
