Advanced Semiconductor
IBM Announces World's First Sub-1nm Chip Technology with Nanostack Architecture
IBM has unveiled the world's first sub-1 nanometer chip technology, featuring a transistor architecture at 0.7 nanometers or 7 angstroms, a scale approaching the size of individual atoms. The technology is built around a new "nanostack" 3D architecture developed through advances in thin die
5 min read
ASML, TSMC and imec Present 300mm Process for 2D-Material n and pFETs Achieving 50nm Contacted Poly Pitch
At the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, ASML, TSMC and imec presented a novel 300mm integration route for 2D-material based n and pFETs. The route produced scaled nFETs with MoS2 channels and pFETs with WS2 or WSe2 channels at a contacted poly pitch of 50nm. These
4 min read
Imec and EV Group Achieve Wafer-to-Wafer Hybrid Bonding at 200nm Interconnect Pitch with Sub-40nm Overlay Accuracy
Imec and EV Group (EVG) have demonstrated a wafer-to-wafer hybrid bonding technology with 200nm Cu interconnect pad pitch. The result was obtained on a test vehicle featuring four layers of routable interconnects pre-processed on each wafer prior to bonding. A post-bond Cu pad-to-pad overlay vect
4 min read
CEA-Leti Reports 1 μm Pitch D2W Hybrid Bonding Technology for 3D Semiconductor IC Packaging at ECTC 2026
CEA-Leti has demonstrated a functional test vehicle that uses die-to-wafer (D2W) hybrid bonding at pitches down to 1 μm. The results were presented at the Electronic Components and Technology Conference (ECTC) 2026. The work targets high-performance computing, advanced smart-vision syst
4 min read
Exascale Microelectronics Simulation Suite MicroEleX Offers Four GPU-Accelerated Codes for Ferroelectrics, Quantum Transport, Electrodynamics and Micromagnetics
The MicroEleX software package, developed under the U.S. Department of Energy’s Exascale Computing Project, offers a collection of open-source, GPU-scalable simulation tools built on the AMReX adaptive mesh refinement framework for semiconductor and microelectronics applications. The
4 min read
SCREEN and IBM Collaborate on High NA EUV Lithography Cleaning Process Development
SCREEN Semiconductor Solutions Co., Ltd. and IBM have entered into an agreement to develop cleaning processes for next-generation EUV lithography, focusing on High NA (High Numerical Aperture) EUV technology. This collaboration extends a partnership spanning over a decade, previously centered on
2 min read
3DIC Test Chip Tape-Out Advances Alchip’s Ecosystem for AI and HPC ASICs
Alchip Technologies, a high-performance and AI computing ASIC provider, has completed a 3DIC test chip tape-out, validating its 3DIC ecosystem. The test chip demonstrates an integrated 3DIC solution, including CPU/NPU core, UCIe and PCIe PHY, Lite-IO infrastructure, and third-party IP.
3 min read
izmomicro’s Silicon Photonics Packaging Breakthrough Adding to India’s Semiconductor Innovation
izmomicro, a division of izmo Ltd., has achieved a significant milestone in silicon photonics packaging, marking a pivotal advancement for India’s semiconductor industry. The company has developed a high-density silicon photonics packaging platform supporting 32-channel fiber input and outp
2 min read
xLight Secures $40M Series B to Advance EUV Laser Technology for Semiconductor Manufacturing
xLight, a Palo Alto-based company developing high-power lasers, has raised $40 million in a Series B funding round led by Playground Global, with participation from Boardman Bay Capital Management, Morpheus Ventures, and others. The capital will support the design and construction of a full-scale
3 min read
Metasurface Optics Market Expands as STMicroelectronics and Metalenz Ink New License Agreement
STMicroelectronics, and Metalenz, a pioneer in metasurface optics, have signed a new license agreement to advance the adoption of metasurface optics in consumer, automotive, and industrial markets. The agreement enables STMicroelectronics to utilize Metalenz’s intellectual property to produ
2 min read
JNTC Launches TGV Glass Substrate for Advanced Semiconductor Packaging
South Korea based JNTC introduced its Through-Glass-Via (TGV) glass substrate at a product launch event on June 30 at the Korea Exchange Conference Hall, attended by over 200 journalists and investors. The event, themed "Carving Semiconductors into Glass, the Dream Material," highlighted the subs
2 min read
AI-Driven Demand and Global Investments Propel Advanced IC Substrate Market to $31 Billion by 2030
Yole Group has released its Status of the Advanced IC Substrates Industry 2025 report, projecting the advanced IC substrate market, encompassing organic advanced IC substrates (AICS), glass core substrates (GCS), substrate-like PCBs (SLP), and embedded die (ED) technologies, to reach $31 billion
3 min read
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