3DIC Test Chip Tape-Out Advances Alchip’s Ecosystem for AI and HPC ASICs

Alchip Technologies, a high-performance and AI computing ASIC provider, has completed a 3DIC test chip tape-out, validating its 3DIC ecosystem. The test chip demonstrates an integrated 3DIC solution, including CPU/NPU core, UCIe and PCIe PHY, Lite-IO infrastructure, and third-party IP. 

The test chip, featuring a 3nm top die and a 5nm base die assembled with TSMC’s SoIC®-X packaging technology, was designed to evaluate power density and thermal dissipation challenges in 3D integration. It provides insights for future 3DIC designs using 2nm and 3nm stacked chiplets. The top die includes a CPU, NPU core, and high-power logic, while the base die incorporates a network-on-chip, L3 cache, and interface IP, connected via APLink-3D Lite IO.

The tape-out validated critical 3DIC capabilities, including cross-die synchronous die-to-die IP, design-for-test strategies with redundancy and repair, signal and power integrity analysis, thermal and mechanical simulations, and 3D physical design implementation. The dual-die design required updated EDA tools and methodologies for co-design, with sign-off ensuring electrical, timing, and mechanical integrity.

Alchip achieved a die-to-die latency of 40 picoseconds, enabling timing paths across dies without performance degradation. A 3D clocking structure ensured coherent operation with minimal timing skew. The...