Imec and EV Group (EVG) have demonstrated a wafer-to-wafer hybrid bonding technology with 200nm Cu interconnect pad pitch. The result was obtained on a test vehicle featuring four layers of routable interconnects pre-processed on each wafer prior to bonding. A post-bond Cu pad-to-pad overlay vector below 40nm was achieved for 100% of the dies across the full 300mm wafer.
The demonstration was presented at the 2026 IEEE Electronic Components and Technology Conference (ECTC). It advances the requirements for logic-to-logic and memory-to-logic tier stacking under imec’s CMOS 2.0 scaling paradigm. In this approach, a system-on-chip (SoC) is partitioned into heterogeneous functional tiers reconnected through 3D interconnects, including potential splitting of logic into high-drive and high-density layers that demand high interconnect density.
The process used SiCN as the dielectric material and an optimized chemical mechanical polishing (CMP) step prior to bonding to achieve high across-wafer uniformity and controlled Cu pad recess. Additional contributors to the overlay accuracy included an improved Cu pad design and pre-bond lithography corrections. EVG’s GEMINI FB hybrid and fusion wafer bonding system was utilized for the bonding process.
Zsolt Tokei, imec fellow and program director of 3D system integration, said: “This breakthrough fine-pitch hybrid bonding result was achieved by co-optimizing all the critical elements of imec’s hybrid bonding process flow. These include, among others, the use of SiCN as the dielectric material (as pioneered by imec) and a chemical mechanical polishing (CMP) step prior to bonding. The latter was optimized for high across-wafer uniformity to produce extremely flat dielectric surfaces while achieving a controlled few nanometers of recess for the Cu pads. The high overlay accuracy and control, enabled by EVG’s wafer bonding tool, were additionally facilitated by an improved Cu pad design and by pre-bond lithography corrections.”
Tokei added that the teams will continue to advance the hybrid bonding roadmap below 200nm interconnect pitch for demanding logic-to-logic and memory-to-logic applications, with further work on overlay performance in collaboration with EVG.
“The long-standing collaboration with imec reflects the important role that wafer bonding continues to play in enabling next-generation semiconductor devices,” stated Paul Lindner, executive technology director at EV Group. “Over more than three decades of working together, we have demonstrated how close collaboration between equipment suppliers and leading research organizations such as imec can drive meaningful advances in process technology.”
The results are detailed in the ECTC paper titled ‘Wafer-to-wafer hybrid bonding technology with 200nm interconnect pitch’ by S. Van Huylenbroeck et al. (Session 26, May 29).
