ASML, TSMC and imec Present 300mm Process for 2D-Material n and pFETs Achieving 50nm Contacted Poly Pitch

At the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, ASML, TSMC and imec presented a novel 300mm integration route for 2D-material based n and pFETs.

The route produced scaled nFETs with MoS2 channels and pFETs with WS2 or WSe2 channels at a contacted poly pitch of 50nm. These are the first scaled n and pFETs at this pitch to be demonstrated, and they showed good current-voltage characteristics.

The transistors target ultra-scaled logic as well as back-end-of-line and wafer backside applications. 2D transition metal dichalcogenides such as MoS2, WS2 and WSe2 function as atomically thin conduction channels that replace silicon and provide electrostatic channel control with acceptable carrier mobilities at ultra-scaled gate and channel lengths.

The integration delivered three reported outcomes: scaled n and pFETs at 50nm contacted poly pitch; very low off current at zero gate voltage for both transistor types; and WSe2 pFETs performing close to record lab-based devices. Ninety-four percent of the transistors were operational, defined as Imax/Imin greater than 10^5. The n and pFETs were integrated on the same 300mm wafer in a CMOS-like configuration, and the process was described as robust and stable. The flow applies to 2D channel materials beyond MoS2, WS2 and WSe2.

Fabrication followed a reverse thin-film transistor approach. Bottom co...