VLSI
First Semiconductor chip Tape-Out: IC Product Startup’s Survival Test
After months of schematics, simulations, and DRC and LVS checking sleepless nights, a product VLSI startup’s first tape-out marks a key milestone in the tough world of semiconductor design. This is the moment when a chip design transitions from digital blueprints to physical silicon, a proc
6 min read
2nm Chip Design Challenges: Signal Parasitics Impact Performance and Power Efficiency
At deep nodes such as 2nm, signal parasitics create bigger challenges. The electrical characteristics like resistance, capacitance, and inductance pose significant challenges to chip performance, power efficiency, and design complexity. These parasitic effects, arising from the physical layout of
6 min read
3rd IEEE International Conference on Networks, Multimedia, and Information Technology (NMITCON-2025) Successfully Held at NMIT, Bengaluru
On August 1-2, 2025, the Nitte Meenakshi Institute of Technology (NMIT) in Bengaluru hosted the 3rd IEEE International Conference on Networks, Multimedia, and Information Technology (NMITCON-2025). Organized in collaboration with the IEEE Bangalore Section and academic partners, including the Uni
6 min read
Etienne Racine from Siemens EDA shares Advanced Features of Tessent Memory BIST for High-Reliability Applications
In an exclusive interview with Srinivasa Reddy N from EEHerald, Etienne Racine, Product Manager at Silicon Test Solutions, Siemens EDA, introduced two powerful new options for their Tessent Memory BIST tool, designed to enhance testing and reliability for advanced memory technologies. These updat
5 min read
Siemens and SK keyfoundry Launch 130nm Automotive Power Semiconductor PDK for Enhanced Design Optimization
Siemens Digital Industries Software, in collaboration with SK keyfoundry and Korea Siemens EDA, has introduced a 130nm automotive Process Design Kit (PDK) tailored for use with Calibre PERC software. This PDK, one of the first Korean domestic established node processes to support both schematic a
2 min read
ITC India 2025 Showcases Semiconductor Testing Advancements in Bangalore
The International Test Conference (ITC) India 2025, organized by IEEE, concluded on July 22, 2025, in Bangalore showing the path to advancement of chip- testing in India’s semiconductor testing ecosystem. Held from July 20 to 22, the event brought together engineers, indus
8 min read
Post Silicon Testing: Janusz Rajski Shares Key Trends on Transformative DFT Technologies on the Sidelines of Event ITC India 2025
In the AI accelerated world of semiconductor chip design, ensuring the reliability and performance of increasingly complex chips is critical. Design for Test (DFT) technologies play a important role in this process, and few have shaped the field as profoundly as Janusz Rajski, a leading expert at
6 min read
Synopsys Acquires Ansys, Expanding AI-Driven Engineering Solutions Market to $31 Billion
Synopsys finalized its acquisition of Ansys on July 17, 2025, as announced on January 16, 2024. The transaction merges Synopsys’ expertise in silicon design and intellectual property with Ansys’ capabilities in simulation and analysis, targeting innovation in AI-powered products. The
2 min read
Xcelium Distributed Simulation App Boosts Multi-Die Verification Speeds by Up to 3X for AI and Chiplet Designs
Cadence has introduced the Xcelium Distributed Simulation App as part of its Xcelium Logic Simulator to address the computational demands of multi-die system simulations for AI, high-performance computing, automotive, and mobile applications. The app accelerates verification by up to 3X compared
2 min read
Build Your Chip Dream: India’s Affordable Semiconductor Fab Opens Doors for Innovators
India’s semiconductor industry is rising in mutitple fronts, opening range of opportunities for startups and SMEs to innovate in chip design and manufacturing. This article explores how Rajkot, Gujarat based Monk9 Tech, a pioneering low-volume fab in India producing chips at 130nm to 350nm
9 min read
Electronic System Design Industry Sees 12.8% Revenue Growth to $5.1 Billion in Q1 2025, Driven by Semiconductor IP and Regional Expansion
The Electronic System Design (ESD) industry reported a 12.8% revenue increase to $5,098.3 million in Q1 2025, up from $4,521.6 million in Q1 2024, according to the ESD Alliance’s Electronic Design Market Data (EDMD) report. The four-quarter moving average for the industry rose by 12.6%, ref
2 min read
Socionext Releases White Paper on High-Bandwidth Switch Fabric SoC Design Methodology
Socionext has announced the release of a white paper titled "Optimizing High-Bandwidth Switch Fabric SoC Design: Minimizing Implementation Risks, Ensuring First-Pass Success, and Accelerating Time-to-Market." The document addresses the increasing complexity of switch fabric System-on-Chip (SoC) d
2 min read
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