Etienne Racine from Siemens EDA shares Advanced Features of Tessent Memory BIST for High-Reliability Applications

In an exclusive interview with Srinivasa Reddy N from EEHerald, Etienne Racine, Product Manager at Silicon Test Solutions, Siemens EDA, introduced two powerful new options for their Tessent Memory BIST tool, designed to enhance testing and reliability for advanced memory technologies. These updates target high-reliability markets, including automotive and other critical applications, addressing the growing demand for robust memory solutions in semiconductors.

ECC-Aware Repair Support for Enhanced Reliability

The first major enhancement to Tessent Memory BIST is its ECC (Error Correction Code)-aware repair support. Racine explained that this feature enables seamless integration with memories equipped with ECC, allowing it to coexist with repair capabilities. "If you have a memory that comes with ECC, we can support its presence and make it coexist with the repair capabilities," Racine told Srinivasa. This ensures that ECC logic is factored into repairs, maintaining data accuracy and integrity.

ECC as a unique selling point for semiconductor companies: This capability is particularly valuable for applications requiring high reliability, such as automotive microcontrollers. Racine highlighted that the tool supports diverse use cases: some applicati...