VLSI

Should You Build Your Own AI-Assisted Silicon IP and EDA Tools? A Brutally Honest Analysis
VLSI

Should You Build Your Own AI-Assisted Silicon IP and EDA Tools? A Brutally Honest Analysis

The question lands on the desk of every engineering VP at a growing fabless firm, usually after a painful licensing renewal: Do we keep paying ARM and Synopsys indefinitely, or do we build our own stack? It is not a hypothetical anymore. India's Saankhya

13 min read
CDAC Offers VEGA RISC-V Processors and Peripheral IPs Free for MPW
VLSI

CDAC Offers VEGA RISC-V Processors and Peripheral IPs Free for MPW

CDAC has announced that its VEGA processors and peripheral IPs are now available free of cost for multi-project wafer (MPW) runs. The organization is also providing 100% free technical support to all licensing partners. The VEGA series consists of processors developed under the microproces

4 min read
Soliton Demonstrates Language-Agnostic, Scalable Test Solutions Powered by AI
VLSI

Soliton Demonstrates Language-Agnostic, Scalable Test Solutions Powered by AI

Soliton Technologies, a leading provider of software-powered post-silicon test and automation services, showcased its advanced solutions for semiconductor validation at the IESA Vision Summit 2026, held on February 25–26 at The Leela Bhartiya City Convention Centre. The company speci

3 min read
SoC Design: The Hidden PPA Killer Lurking in Every Clock Tree: Why Buffer Size Still Rules Advanced Node VLSI Chip Design
VLSI

SoC Design: The Hidden PPA Killer Lurking in Every Clock Tree: Why Buffer Size Still Rules Advanced Node VLSI Chip Design

The role of buffer size in System-on-Chip (SoC) and complex VLSI designs is one of the most critical yet subtle optimization levers available to physical design engineers. Buffers (including inverters used as buffers) are inserted throughout the chip to manage signal integrity, timing, power, are

21 min read
GlobalFoundries Acquires Synopsys Processor IP Business Amid RISC-V and AI Trends
VLSI

GlobalFoundries Acquires Synopsys Processor IP Business Amid RISC-V and AI Trends

Synopsys has entered into a definitive agreement to sell its Processor IP Solutions business to GlobalFoundries.The transaction allows Synopsys to focus its IP resources on interface and foundation IP while pursuing AI-driven opportunities from cloud to edge in sectors including high-performance

3 min read
VLSI Chip Design and Tape-out: IHP Advances Open-Source Chip Fabrication with 2026 MPW Runs and Upcoming PDK Release
Semiconductor Foundry

VLSI Chip Design and Tape-out: IHP Advances Open-Source Chip Fabrication with 2026 MPW Runs and Upcoming PDK Release

Germany based Leibniz Institute for High Performance Microelectronics (IHP) continues to democratize access to cutting-edge silicon fabrication through its open-silicon Multi-Project Wafer (MPW) program, with several affordable runs scheduled for 2026. This program targets academics, start

3 min read
Electronic System Design Industry Revenue Hits $5.1 Billion in Q2 2025, Driven by EDA and Regional Growth
VLSI

Electronic System Design Industry Revenue Hits $5.1 Billion in Q2 2025, Driven by EDA and Regional Growth

The Electronic System Design (ESD) industry reported an 8.6% revenue increase to $5,089.4 million in Q2 2025, up from $4,685.5 million in Q2 2024, according to the latest Electronic Design Market Data (EDMD) report by the ESD Alliance, a SEMI Technology Community. The four-quarter moving average

2 min read
Synopsys Expands India Presence with New Bengaluru R&D Hub on 30-Year Milestone
VLSI

Synopsys Expands India Presence with New Bengaluru R&D Hub on 30-Year Milestone

Synopsys marked 30 years of operations in India by opening a new research and development facility in Bengaluru. The inauguration at Bagmane Capital was attended by Synopsys president and CEO Sassine Ghazi and executive chair and founder Dr. Aart de Geus. The 455,000-square-foot facility supports

2 min read
Alphawave Semi Advances AI and HPC with UCIe Chiplet IP on TSMC’s 3DFabric Platform
VLSI

Alphawave Semi Advances AI and HPC with UCIe Chiplet IP on TSMC’s 3DFabric Platform

Alphawave Semi announced successful tape-out of its UCIe 3D IP on TSMC’s SoIC (SoIC-X) technology within the 3DFabric platform. This development builds on the company’s existing UCIe IP subsystems and integrates TSMC’s advanced 3D packaging technology to address performance, pow

3 min read
AI EDA  tools: AutoChip Leverages Large Language Models for Verilog Module Generation
VLSI

AI EDA tools: AutoChip Leverages Large Language Models for Verilog Module Generation

A new tool, AI VLSI semiconductor design EDA tool AutoChip, has been developed to generate functional Verilog modules from initial design prompts and testbenches using large language models (LLMs). The tool, detailed in a paper accepted for publication in the ACM Transactions on Design Automation

3 min read
Addressing the SDC 'Root-of-Trust' Problem in AI-Driven Semiconductor Design
VLSI

Addressing the SDC 'Root-of-Trust' Problem in AI-Driven Semiconductor Design

At DVCon, Dr. Sam Appleton, CEO of Ausdia Inc., delivered a talk on the critical "Root-of-Trust" problem in SDC (Synopsys Design Constraints) flows, shedding light on the challenges and opportunities in AI-driven semiconductor design. As a startup focused on a niche segment of the electronic desi

6 min read
VeriSilicon Launches FD-SOI Wireless IP Platform for IoT and Consumer Electronics Connectivity
VLSI

VeriSilicon Launches FD-SOI Wireless IP Platform for IoT and Consumer Electronics Connectivity

VeriSilicon introduced a wireless IP platform based on GlobalFoundries’ 22FDX (22nm FD-SOI) process technology, designed for developing energy-efficient, integrated chips for IoT and consumer electronics. The platform supports wireless connectivity standards including Bluetooth Low Energy (

2 min read
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