Alphawave Semi Advances AI and HPC with UCIe Chiplet IP on TSMC’s 3DFabric Platform

Alphawave Semi announced successful tape-out of its UCIe 3D IP on TSMC’s SoIC (SoIC-X) technology within the 3DFabric platform. This development builds on the company’s existing UCIe IP subsystems and integrates TSMC’s advanced 3D packaging technology to address performance, power efficiency, and bandwidth demands for datacenter, AI, and HPC applications.

The IP, designed for face-to-face (F2F) configurations, offers a 10x improvement in power efficiency and up to 5x higher signal density compared to traditional 2.5D die-to-die interfaces. It addresses limitations in conventional planar designs, where chip communication is constrained by edge space, impacting bandwidth and functionality. The shift to 3D die stacking enables enhanced bandwidth density and power efficiency, supporting the growing complexity of AI models and the limitations of traditional scaling methods like Moore’s Law.

Alphawave Semi’s UCIe-3D 5nm bottom die incorporates TSVs to provide power and ground to the 3nm top die, supported by a proprietary design flow and methodology for efficient 3D stack construction and verification. Mohit Gupta, Executive Vice President & General Manager at Alphawave Semi, stated, “This successful tape-out represents a significant milestone for Alphawave Semi and our AI platform. By combining our high-speed 3D UCIe IP with T...