AI EDA tools: AutoChip Leverages Large Language Models for Verilog Module Generation

A new tool, AI VLSI semiconductor design EDA tool AutoChip, has been developed to generate functional Verilog modules from initial design prompts and testbenches using large language models (LLMs). The tool, detailed in a paper accepted for publication in the ACM Transactions on Design Automation of Electronic Systems (TODAES) special issue on Large Language Models for Electronic System Design Automation, integrates feedback from compilation and simulation errors to refine the generated Verilog code.

AutoChip, authored by Jason Blocklove, Shailja Thakur, Benjamin Tan, Hammond Pearce, Siddharth Garg, and Ramesh Karri, is available under the Apache License. The tool’s repository can be accessed at  github. The associated research paper, titled “Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback,” is published on arXiv.

To operate AutoChip, users need Python 3.10 or newer, pip for dependency installation, and Icarus Verilog. Installation involves cloning the repository, setting up a virtual environment, and installing required Python packages via `pip3 install -r requirements.txt`. Users must also configure API keys for supported LLMs, such as OpenAI (OPENAI_API_KEY) or Anthropic (ANTHROPIC_API_KEY).

Au...