VLSI Chip Design and Tape-out: IHP Advances Open-Source Chip Fabrication with 2026 MPW Runs and Upcoming PDK Release

Germany based Leibniz Institute for High Performance Microelectronics (IHP) continues to democratize access to cutting-edge silicon fabrication through its open-silicon Multi-Project Wafer (MPW) program, with several affordable runs scheduled for 2026.

This program targets academics, startups, innovators, and open-source developers, offering low-cost tape-out in advanced 130nm BiCMOS and CMOS nodes.

Designs released under Apache 2.0 license qualify for the lowest pricing, with requirements for open-source EDA tool compatibility and GitHub publication for transparency and reproducibility.

Private IP submissions receive a 20% discount.

Upcoming 2026 open-source MPW runs include:

- March 30, 2026: SG13CMOS and SG13CMOS5L (registration deadline: March 2, 2026) — €1,500/mm² for SG13CMOS; €0/mm² for educational SG13CMOS5L designs.
- July 13, 2026: SG13CMOS5L (deadline: June 29, 2026) — €1,500/mm².
- October 6, 2026: SG13G2 (deadline: September 21, 2026) — €2,800/mm².

Standard inclusions: 40 bare die samples, optional wafer rental and packaging.

The technologies feature high-speed SiGe heterojunction bipolar transistors (HBTs) up to 350 GHz f_T / 450 GHz f_max in SG13G2, with ongoing development toward even higher performance.

IHP's open-source PDK for SG13G2 is a...