The International Test Conference (ITC) India 2025, organized by IEEE, concluded on July 22, 2025, in Bangalore showing the path to advancement of chip- testing in India’s semiconductor testing ecosystem. Held from July 20 to 22, the event brought together engineers, industry leaders, and academic researchers to discuss advancements in post-silicon testing, a critical component of the rapidly evolving semiconductor industry in India. The conference featured a diverse mix of presentations, keynotes, panel discussions, and a hackathon, showcasing cutting-edge solutions and engaging collaboration.
Pic: Test Event Corridors
ITC India 2025 highlighted the growing importance of post-silicon testing in India’s semiconductor ecosystem. Companies such as Tessolve, Advantest, Siemens, Caliber Interconnects, Synopsys, Cadence, Soliton, and Anora showcased their expertise through dedicated booths. Tessolve presented end-to-end silicon and system solutions, from design to production, emphasizing custom IC design and test engineering. Advantest focused on automation in silicon validation and SoC test engineering with its SiConic solutions. Siemens highlighted its Tessent DFT solutions for smarter chip testing, while Caliber Interconnects displayed innovations in semiconductor testing and board design. Synopsys, a Gold Sponsor, demonstrated advancements in SLM high-speed access and test IP, and Cadence showcased DFT solutions for high coverage and reduced test time. Soliton and Anora contributed expertise in automated test equipment and post-silicon analysis, respectively.
Keynotes:
Pic: Janusz Rajski
The conference featured keynote sessions addressing critical challenges in semiconductor testing. Janusz Rajski, a pioneer in design and test automation, opened the event with a talk on next-generation test strategies and resilient silicon architectures. Read an exclusive article titled "Post Silicon Testing: Janusz Rajski Shares Key Trends on Transformative DFT Technologies on the Sidelines of Event ITC India 2025"
Pic: Raja Swaminathan
Raja Swaminathan from AMD discussed advanced packaging and chiplet architectures, focusing on scalability in high-performance computing.
Pic: India's Fabless Innovation bottlenecks slide by Rajesh, Tessolve
Rajesh V from Tessolve shared insights on bridging design and deployment through robust DFT strategies. Nitza Basoco from Teradyne emphasized the importance of early test planning in her talk, “The Right Testing Strategy Can Save Designs,” highlighting cost reduction and design reliability. Suresh Babu K from Caliber Interconnect Solutions explored the societal impact of semiconductor advancements, while Dr. Sreejit Chakravarty from Ampere Computing addressed strategies to reduce silent data corruption and quality escapes in high-performance computing. Adam Cron from Synopsys delivered a distinguished talk on “The Standard for Test – IEEE 1838 for 3D IC,” discussing standardized test access for 3D IC architectures.
Panel Discussion on India’s Test Ecosystem
A key highlight was a panel discussion titled “India's Semiconductor Test Ecosystem: Building for Scale and Innovation,” moderated by Venkata Rangam Totakura from Infineon. Panelists, including Ruchir Dixit (Siemens), Paresh Bharkhada (Teradyne), Anand Muthaiah (Tessolve), and Senthilkumar Dhamodharan (Caliber Interconnect), explored India’s role in global test innovation. The discussion emphasized the need for skilled talent, robust infrastructure, and stronger industry-academia partnerships to build a scalable test ecosystem.
Pic: Panel Discussion
Hackathon and Award-Winning Research
The ITC India 2025 Hackathon recognized outstanding contributions from academic teams. First place was awarded to Jagadeesh Pradhani, Suresh G Kini, and L Ashok Kumar Reddy from KLE Technological University. Second place went to Chaitra YG and Hady Rahman AV from BMS College of Engineering, while third place was secured by Dr. Babita Jajodia, Bheemuni Harshavardhan Reddy, and K. Shruthi from the Indian Institute of Information Technology, Guwahati. An honorable mention was given to Ila Vaghela, Amansinh M Chudasama, and Aashvi Patel from Einfochips (An Arrow Company) Pvt. Ltd.
Pic: Hackthon winners
Several research papers were recognized for their contributions. Amol G. Patil, Suhas B. Shirol, and Vikas K. R from KLE Technological University received the Best Academia Research Track Paper Award for “Implementation of Memory Built-In Self-Test.”
Pic: TRC Best Paper Award winners
Ankit Bansal (Synopsys, India) and Ajay Chauhan (Marvell, India) won the TRC Best Paper Award for “Incremental Memory Repair Techniques with Synopsys SMS for Multi-hierarchy Server Architecture.” Akhilesh Shenoy and Shradha Todi earned the Best Poster Award for “Leveraging TMU Sensors for Software-Driven Thermal Mapping and Visualization in SoCs.”
Pic: Posters by Akhilesh Shenoy(Samsung), Tellakunta Karthik Guptha and Racha Ganesh (CVR College of Engineering), and Mega Goswami (Nvidia)
Additional nominations for Best Paper Awards included works on low pin-count SoC testing, reliability through accelerated aging, high-bandwidth IJTAG, and machine learning-based self-testing for oscillators. The ITC India Best Papers 2024 awards went to Aneri Jain, Wilson Pradeep, and Andreas Glowatz for “Optimized Timing Aware ATPG for At-Speed Test of Cell Internal Faults,” with honorable mentions for papers on FPGA-based emulation and concurrent low-power testing for safety-critical SoCs.
Technical Sessions and Industry Insights
Technical sessions included Pradeep Nagaraj from Cadence discussing the evolution of Design for Test (DFT) methodologies. Synopsys presented a paper on low-shift power ATPG decompression and a Test Reality Check session on incremental memory repair techniques using Synopsys SMS, further highlighting advancements in test automation and reliability.
ITC India 2025 underscored India’s growing prominence in the global semiconductor testing landscape. With a focus on innovation, collaboration, and skill development, the event provided a platform for engineers, researchers, and industry leaders to address challenges and explore solutions in post-silicon testing, paving the way for a robust and scalable semiconductor ecosystem in India.
