Cadence has introduced the Xcelium Distributed Simulation App as part of its Xcelium Logic Simulator to address the computational demands of multi-die system simulations for AI, high-performance computing, automotive, and mobile applications. The app accelerates verification by up to 3X compared to traditional methods, enabling faster simulation of chiplet-based designs.
The Xcelium Distributed Simulation App utilizes multicore technology to divide large-scale simulations into independent tasks processed simultaneously as separate executables. This approach enhances efficiency, reduces resource demands, and achieves simulation speeds up to 3X faster. It also lowers costs by up to 5X in high-capacity server environments by optimizing workloads.
Alok Jain, corporate vice president of research and development at Cadence, stated that the app enables design teams to address verification challenges for complex semiconductor designs with improved speed and efficiency. Early adopters, including Samsung Semiconductor, have used the app to reuse single-die testbenches for multi-die verification, reducing time to market. Garima Srivastava, director of chip design verification at Samsung Semiconductor, noted that collaboration with Cadence enhanced simulation performance for multi-die and multi-chip designs while maintaining performance standards.
The Xcelium Logic Simulator, with ongoing updates, supports verification needs for complex chip designs. More details are available on the Cadence Xcelium Logic Simulator product page.
