Cadence announced an expanded partnership with TSMC to accelerate 3D-IC and advanced-node technology development, focusing on certified design flows, silicon-proven IP, and ongoing technology collaboration. As a key IP provider for TSMC’s N2P, N5, and N3 process nodes, Cadence delivers AI-driven design solutions for chiplets, SoCs, advanced packaging, and 3D-ICs.
Cadence provides certified tools and IP for TSMC’s N2P and A16 processes, including digital, custom/analog design, and thermal analysis solutions. Its TSMC9000 pre-silicon-certified DDR5 12.8G IP for N2P supports memory-intensive applications, while AI-driven digital design solutions using large language models enhance design flows for future nodes.
For automotive applications like ADAS, autonomous driving, and software-defined vehicles, Cadence offers certified IP for TSMC’s N5A and N3A processes, including LPDDR5X-9600, PCI Express 5.0, CXL 2.0, 25G-KR, and 10G multi-protocol SerDes, optimized for automotive performance.
Cadence supports TSMC 3DFabric with a comprehensive chiplet design, packaging, and system analysis solution. Its IP portfolio for AI training includes TSMC 9000-certified HBM3E 9.6G in N5/N4P, pre-silicon HBM3E 10.4G in N3P, and Universal Chiplet Express 16G in N3P. The Cadence Integrity 3D-IC Platform enhances quality of results and supports 3Dblox reference flows for chip-package co-design, global resource optimization, and multiphysics convergence analysis.
Cadence’s Virtuoso Studio facilitates analog and RF design migration, reducing turnaround time for advanced and RF nodes. The company also advances TSMC’s compact universal photonic engine and cloud-based design solutions with GPU-accelerated compute for improved efficiency.
This collaboration supports TSMC’s advanced-node technologies, enabling solutions for infrastructure AI, physical AI, and automotive applications.
