Multi-Die Chiplets, AI-Driven Testing & Silent Data Corruption Take Center Stage at International Test Conference 2026

As advanced node manufacturing, heterogeneous integration, and silicon photonics drive exponential growth in testing complexity, industry leaders gathered at the International Test Conference (ITC) 2026 to address critical challenges and emerging solutions in semiconductor test and reliability.

 

Testing remains a vital post-design and post-manufacturing activity to ensure product success and customer trust. However, with massive increases in data volumes, sophisticated processor architectures, higher data speeds, and rising power consumption, test case scenarios have expanded dramatically. Short market windows further intensify the need for “shift left, right, and all around” strategies to detect and manage bugs early.

 

India, playing a key role in semiconductor design and testing, is witnessing heightened demand for specialized skills even as AI tools gain prominence. The conference provided a timely platform for EDA and test companies to showcase innovations to DFT and VLSI test engineers.

 

In a compelling keynote, Yervant Zorian of Synopsys highlighted the rapid industry shift from monolithic dies to multi-die and chiplet-based designs. With systems approaching trillion-transistor complexity and traditional scaling slowing, heterogeneous multi-die architectures integrating CP...