Efinix Announces Titanium Edge FPGA Family for Edge AI Applications

Efinix has announced the Titanium Edge family of FPGAs, designed for demanding edge AI deployments. The new family is built on the company’s Titanium architecture and targets high-growth markets requiring constrained power, size, and security features.The Titanium Edge family addresses five specified areas: power consumption, physical space, I/O performance, reliability, and security.

Power: The devices deliver 50% lower static power compared to the existing Titanium family.
Space: System-in-Package (SiP) variants integrate the FPGA, HyperRAM, and boot flash into a single module, reducing PCB footprint by up to 60% versus discrete designs. Package sizes scale down to 5.5 mm × 5.5 mm.
Performance: Support for up to 2.5 Gbps I/O with MIPI interfaces in x1, x2, x4, and x8 data lane configurations, allowing direct connection for multi-sensor AI pipelines in vision, imaging, and autonomous systems.
Reliability: Includes a dedicated hardware SEU scrubbing engine that continuously monitors and corrects configuration memory against radiation-induced bit flips.
Security: Security variants incorporate post-quantum cryptography aligned with CNSA 2.0 and EU Cyber Resilience Act timelines. Features include ML-DSA-65 (CRYSTALS-Dilithium) signature authentication, AES-256-GCM encryption, RSA-4096 and EC-DSA-384 support, PUF-based key derivation, secure boot with chain-of-trust, TRNG for entropy, full key lifecycle management (rotation, revocation, anti-rollback), and secure debug with JTAG disable.

Sammy Cheung, co-founder and CEO of Efinix, stated that in edge AI, every milliwatt, square millimeter, and attack surface matters, noting the family resulted from customer co-development for constrained deployments.Tony Ngai, co-founder, Co-President, and CTO, described the integration of post-quantum security, hardware SEU scrubbing, and SiP packaging as enabling design for certification through long-term field deployment.Titanium Edge Device Lineup

Ti125: 123,000 Logic Elements (sampling now)
Ti125 SiP: 123,000 Logic Elements with 512Mb HyperRAM and SPI boot flash (sampling August 2026)
Ti95: 93,000 Logic Elements (sampling now)
Ti70: 68,000 Logic Elements (sampling Q4 2026)
Ti70 SiP: 68,000 Logic Elements with 256Mb HyperRAM and SPI boot flash (sampling Q4 2026)
Ti40: 39,000 Logic Elements (sampling Q4 2026)

Security variants for Ti125 and Ti95 are scheduled for Q4 2026 sampling.All devices are supported by the Efinity Integrated Development Environment for RTL-to-bitstream flows. The Efinix ecosystem includes Sapphire SoC solutions for embedded RISC-V AI processing and FPGA fabric-based accelerators for ML-DSA, ML-KEM, SHA-3, and SHAKE algorithms.Evaluation boards, design support, and pricing information are available at www.efinixinc.com.

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