QuickLogic has released an enhanced eFPGA Hard IP that builds on its silicon-proven technology for GlobalFoundries 12LP. The release includes improved performance and area efficiency, scales beyond 250K LUTs, and adds enhanced DSP and optional configuration bit health monitoring.
Key new features include:
- A new DSP Multiply-and-Accumulate (MAC) unit, with enhanced preadder, cascade connections, and SIMD functionality, for phased array radar, electronic warfare, wireless infrastructure, satellite communications, and imaging algorithms.
- The eFPGA fabric can scale to support more than 250,000 LUTs.
- An optional Configuration Bit Health Monitor that detects and corrects configuration bit errors induced by Single Event Upsets (SEUs) while the eFPGA user design is active.
Andy Jaros, VP of IP Sales at QuickLogic, said: “Customers increasingly want the flexibility to adapt hardware functions after tape-out without sacrificing the performance, power and area advantages of an ASIC. Our enhanced eFPGA Hard IP for GF 12LP gives SoC developers greater scalability and signal-processing capability, while our optional Configuration Bit Health Monitor adds another level of reliability for the most demanding applications.”
QuickLogic's eFPGA Hard IP enables programmable logic to be embedded directly within an SoC, allowing critical hardware functions, algorithms and interfaces to be updated post-manufacturing. The architecture can be scaled and configured with user-defined combinations of LUT, BlockRAM and DSP resources, with complete RTL-to-bitstream development support through QuickLogic's Aurora and AuroraPRO tools.
QuickLogic is a Silver Sponsor of GlobalFoundries Technology Summit (GTS) North America. The event is at the Santa Clara Marriott in Santa Clara, CA, Booth #11 in the Partner Pavilion, on September 2, 2026. Attendees can meet with the QuickLogic team regarding the enhanced GF 12LP eFPGA Hard IP and QuickLogic's embedded FPGA solutions.
