Arteris, Inc., a provider of system IP for semiconductor development, announced an expansion of its multi-die solution to support chiplet-based designs. The solution addresses the increasing computational demands of AI, which are outpacing traditional monolithic die designs due to the slowing of Moore’s Law. It includes technologies for scalable, high-performance computing and automotive-grade designs.
The solution features silicon-proven non-coherent FlexNoC IP, which supports standards-based die-to-die communication and integrates with third-party controllers and PHYs. New cache-coherent Ncore NoC IP enables seamless cache operations across multiple chiplets. The Magillem Connectivity and Registers automation tools streamline SoC assembly and hardware-software integration, reducing manual integration risks.
Arteris’ solution supports the Universal Chiplet Interconnect Express (UCIe) specification, Arm AMBA protocols, PCIe, and integration with physical IPs from EDA and foundry partners, including Cadence, Synopsys, and global fabs. Collaborations include Arm for AMBA CHI C2C specification support, Cadence for optimized IP and EDA tool flows, Renesas for its R-Car Gen 5 SoC platform for ADAS, RISC-V partners like Andes, SiFive, and Tenstorrent for domain-specific IPs, and Synopsys for UCIe-compliant multi-die designs.
The solution aims to reduce chiplet and SoC design time while optimizing power, performance, and area. It is available now to early access partners, with more information at arteris.com/multi-die
