VLSI Course
Semiconductor IP for Advanced 2nm SoCs in the Silicon AI Era: Winners, Money-Spinning IPs, and Rising Trends
As we enter late 2025, the semiconductor industry is entering 2nm era enabling further growth of chips used in artificial intelligence (AI) systems and also for various other applications such as smart phone SoC and personal computer
6 min read
2nm Chip Design Challenges: Signal Parasitics Impact Performance and Power Efficiency
At deep nodes such as 2nm, signal parasitics create bigger challenges. The electrical characteristics like resistance, capacitance, and inductance pose significant challenges to chip performance, power efficiency, and design complexity. These parasitic effects, arising from the physical layout of
6 min read
Module 3a: Introduction to VLSI and Digital Design
For young electronics engineering graduates in India, a career in VLSI design offers excellent long-term growth and the satisfaction of working in a core electronics field. However, VLSI design demands a stro
36 min read
ITC India 2025 Showcases Semiconductor Testing Advancements in Bangalore
The International Test Conference (ITC) India 2025, organized by IEEE, concluded on July 22, 2025, in Bangalore showing the path to advancement of chip- testing in India’s semiconductor testing ecosystem. Held from July 20 to 22, the event brought together engineers, indus
8 min read
RISC-V Multi-Core and Many-Core Architectures
The open-source RISC-V instruction-set architecture has moved from academic curiosity to mainstream technology in barely a decade, shipping more than 10 billion cores by 2022 and expanding at a pace that outstrips earlier ISAs such as x86 and ARM. Market analysts forecast an add
65 min read
Why OpenROAD is evolving well: A 2025 perspective
The OpenROAD project (Open Real-time Optimized Autonomous Design) is rapidly transforming the landscape of electronic design automation (EDA). Launched in 2018 under DARPA’s Electronics Resurgence Initiative, OpenROAD set out to democratize chip design by creating a fully autonomous, open
22 min read
DVCon U.S. 2026 opens call for extended abstracts, workshops, and tutorials
The Design and Verification Conference and Exhibition United States (DVCon U.S.) 2026, sponsored by Accellera Systems Initiative, has announced its call for extended abstracts, workshop, and tutorial proposals. The event is scheduled for March 2-5, 2026, at the Hyatt Regency Hotel in Santa Clara,
2 min read
Chip design EDA: The three popular and latest P&R tools for advanced nodes including open-source
In electronic design automation (EDA) for deep-node digital Very Large Scale Integration (VLSI) chip design, place and route (P&R) tools are absolute necessary for converting logical designs into physical layouts optimized for performance, power, and area (PPA). As process n
13 min read
Basic introduction to complete VLSI semiconductor chip design covering everything in few hours of reading
Fundamentals of VLSI Semiconductor Chip Design: A quick but fairly comprehensive introduction
61 min read
Why engineers going for FPGA rather than ASIC?
At the latest semiconductor IC fabrication process nodes of 45nm and below, the number of logic gates in an FPGA exceeds 5million giving ample space for designing logic functional blocks for today's SoCs (System on Chip). Nearly every FPGA Company provides silicon, software, and hardware referenc
4 min read
Our Editors dive into topical news, new products, and discuss the shifting architecture of the global semiconductor industry.
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