Cadence has announced an expanded partnership with TSMC to deliver advanced capabilities for AI and HPC designers. The company has achieved tool certification for TSMC's advanced A14 process, demonstrated an industry-leading UALink solution in TSMC N3P, and introduced new silicon-proven IP for the N3P and N2P technologies. Through the partnership, the two companies are enabling agentic AI chip and 3D-IC design flows across TSMC's N3, N2, A16, and A14 process technologies, including 3DFabric support for wafer-scale systems with hundreds of chiplets.
Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence, said the partnership continues to deliver breakthrough innovations that help leading-edge customers accelerate their most advanced designs, and that AI-driven design flows, silicon-proven IP, and 3D-IC solutions are helping customers reach the market faster with better PPA. Aveek Sarkar, director of TSMC's Ecosystem and Alliance Management Division, said TSMC and its Open Innovation Platform partners such as Cadence are addressing the key demands of semiconductor development to achieve higher performance and energy efficiency in AI systems, and that broad collaboration on AI-based solutions is speeding up their mutual customers' path to expanding AI with leadership silicon.
Cadence's digital full flow, signoff flow, and custom and analog flows are now certified for TSMC's A16 and A14 processes. The digital flow includes the Innovus Implementation System, the Cerebrus Intelligent Chip Explorer for DTCO, and enhanced signoff tools such as Tempus, the EMX Planar 3D Solver, Voltus, Quantus, Pegasus, and the Liberate Characterization Portfolio, along with the Genus Synthesis Solution. For custom and analog design, Virtuoso Studio offers design-rule-correct layout generation and automated design migration to A16 and A14, cutting iterations by up to 2.5X and improving first-pass success for AI, HPC, and mobile SoCs. On the IP side, UCIe-64G has taped out on A14, LPDDR6 IP is in development, and a wide selection of HPC and AI memory IP and other protocols needed for compute chiplets has been prioritized. Artisan Foundation IP and mixed-signal IP for A14, including standard cells, GPIO, and memory compilers for HPC, AI, and networking, are also in development and expected in Q4 2026.
For N2P, Cadence's analog, digital, and signoff flows are certified, and the Virtuoso Layout Suite now includes enhanced connectivity models that provide a production-ready custom design environment for quicker design starts. The certified flows should enable faster tape-outs and better designer productivity. IP already taped out on N2P includes DDR5, LPDDR5, and PCIe 6.0, while PCIe 3.0 IP is expected to tape out in Q4 2026. UCIe-64G IP on N2P silicon is in the testing lab and has been characterized on N3P.
Cadence has also expanded its 3DFabric and TSMC-COUPE support for scaling to hundreds of chiplets. Its solutions now support the full TSMC SoW-X design flow with hundreds of chiplets and millions of bumps, as well as the design of 5X reticle-size CoWoS-L-style advanced packages. Using Integrity 3D-IC for system planning and assembly, designers can integrate key components such as SoIC, eDTC, MIMCap, IVR, the HBM logic base die, and the substrate. A pre-simulation-driven, die-to-die auto-routing flow is now certified with the Allegro Substrate Router and the OmniRoute Advanced Interconnect Router, automatically deriving signal-integrity-optimized routing strategies across all CoWoS architectures and targeting UCIe requirements. TSMC-COUPE, the Compact Universal Photonic Engine for high-bandwidth photonic-to-silicon connectivity, is enabled for integration with Cadence's 224G SerDes IP, which is aligned with the UALink, ESUN, UltraEthernet, and CPO ecosystems and complements a portfolio that includes HBM4/4E, LPDDR6/5X, DDR5-MRDIMM, PCIe 7.0, and UCIe 64G.
Global Unichip Corp. (GUC) uses Cadence solutions to deliver advanced custom silicon for AI accelerators and hyperscale systems on TSMC's leading-edge processes, and says Cadence-driven automation helps reduce schedule risk for new process technology engagements. Louis Lin, senior vice president at GUC, noted that as designs scale to nodes such as N3P and N2P, success depends on tightly optimized execution, especially for early adopters where schedule risk is highest, and that Cadence provides the predictability, performance, and silicon correlation needed to tape out complex designs on TSMC's most advanced nodes. The innovations from the collaboration was showcased at the 2026 TSMC North America OIP Ecosystem Forum on September 23 at the Santa Clara Convention Center.
