Researchers at the Indian Institute of Science (IISc) have published findings from a two-part study on gallium nitride (GaN) power transistors, focusing on improving gate design to address limitations in threshold voltage and leakage current.
GaN transistors can reduce energy losses and decrease the size of power converters and power electronics modules by up to three times compared to existing solutions. However, commercial p-GaN gate transistors typically exhibit a low threshold voltage of 1.5–2 V and begin leaking current above 5–6 V, which has limited wider adoption in applications such as electric vehicles (EVs) and data centers.
The IISc team, led by Mayank Shrivastava, Professor and Chair at the Department of Electronic Systems Engineering (ESE), investigated the physics governing gate control and threshold voltage determination.
In the first study, the researchers fabricated device variants using the same commercial-grade epitaxial stack but with controlled differences in gate metal stack, p-GaN doping activation, thickness, and sidewall passivation. Through electrical measurements, physics-based analytical modeling, computational simulations, and microscopy, they identified two distinct operating modes: fully depleted and partially depleted p-GaN layer.
In the partially depleted mode, gate leakage pathways were found to influence gate-to-channel coupling and determine threshold voltage. Positive charge accumulation at a critical interface can cause early turn-on, while suppression of this accumulation extends depletion and raises the threshold voltage.
Using these insights, the team demonstrated new metal-based gate stacks (Ti/TiN and Ta/Au) that reduced gate leakage by two to four orders of magnitude (up to 10,000 times), improved threshold voltage stability, and achieved gate breakdown voltages of approximately 11.4 V (Ti/TiN) and 15.5 V (Ta/Au).
In the second study, the researchers introduced a patented AlTiO (aluminium–titanium oxide)-based integrated gate stack on p-GaN/AlGaN/GaN heterostructure. This design suppresses unwanted charge injection and promotes a high-threshold depletion-extension mode. The resulting devices achieved a threshold voltage above 4 V (up to 4.2 V), gate breakdown voltage of 13.6 V, improved threshold stability, and retained strong gate control.
Threshold voltage tuning was governed by p-GaN thickness and doping, leakage characteristics, dielectric crystalline quality, dielectric constant, and p-type properties of AlTiO. High-resolution TEM, C–V/I–V analysis, and TCAD simulations showed that reducing microcrystalline order in AlTiO lowers leakage and dielectric constant, further increasing threshold voltage.
Rasik Rashid Malik, PhD student at ESE and lead author, stated that the advancements could accelerate GaN adoption in EV power converters, server and data center power supplies, renewable energy inverters, and other high-power switching applications requiring reliability and robustness.
The team is working to scale the technology for commercial use through government support, industry licensing, and partnerships.
Mayank Shrivastava noted that achieving higher threshold voltage with low leakage and robust gate overdrive margin is a key factor for the next phase of GaN adoption.
The studies are published as:
- Physical Insights Into Turn-On Mechanisms in p-GaN Gate AlGaN/GaN HEMTs—Part I
- Achieving Ultrahigh Threshold Voltage in Enhancement-Mode AlGaN/GaN HEMTs With an AlxTiyO/p-GaN Integrated Gate Stack—Part II
