Sandisk announced the formation of a Technical Advisory Board to guide the development and strategy of its High Bandwidth Flash (HBF) memory technology. The board, comprising industry experts and senior technical leaders from within and outside the company, includes Professor David Patterson and Raja Koduri as inaugural members, tasked with providing strategic guidance, technical insight, market perspective, and shaping open standards for HBF’s launch.
Professor David Patterson, Pardee Professor of Computer Science, Emeritus at the University of California, Berkeley, and a Google distinguished engineer, will lead the board. He is known for co-developing Reduced Instruction Set Computing (RISC), contributing to Redundant Array of Inexpensive Disks (RAID), and Networks of Workstations (NOW). Patterson co-authored the textbook "Computer Architecture: A Quantitative Approach" and received the 2017 ACM Turing Award. He stated that HBF could enable datacenter AI by providing high memory capacity and bandwidth, allowing inference workloads to scale and potentially reducing costs for AI applications.
Raja Koduri, a computer engineer and executive, previously served as Senior Vice President and Chief Architect at AMD, and Executive Vice President of Accelerated Computing Systems and Graphics at Intel, where he led the development of AMD’s Polaris, Vega, and Navi GPU architectures, and Intel’s Arc and Ponte Vecchio GPUs. In 2023, he founded a generative AI startup for gaming, media, and entertainment, joined the Board of Tenstorrent, and currently serves as Founder/CEO of Oxmiq Labs and Co-Founder of Mihira Visual Studios. Koduri noted that HBF could support edge AI by enabling devices to run sophisticated models locally in real time.
Introduced at Future FWD: Sandisk 2025 Investor Day, HBF is designed to complement High Bandwidth Memory (HBM) for AI inference workloads, offering comparable bandwidth with up to eight times the capacity at a similar cost. It utilizes BiCS technology and CMOS directly Bonded to Array (CBA) wafer bonding, employing proprietary stacking with ultra-low die warpage for 16-high configurations. The architecture was developed over the past year with input from leading AI industry players.
