Cadence and Samsung Foundry expand collaboration to advance SoC, 3D-IC, and chiplet design for AI, automotive, and connectivity applications

Cadence expanded collaboration with Samsung Foundry, incorporating a new multi-year IP agreement and joint development of AI-driven design flows on Samsung’s SF2P, SF4X, and SF5A process nodes. The collaboration focuses on delivering memory and interface IP solutions and advanced design flows for AI data centers, automotive applications, including advanced driver-assistance systems (ADAS), and next-generation RF connectivity.
The multi-year IP agreement includes Cadence’s memory and interface IP solutions for Samsung’s SF4X, SF5A, and SF2P nodes, targeting AI, high-performance computing (HPC), and automotive applications. The SF4X IP portfolio comprises LPDDR6/5x-14.4G, GDDR7-36G, DDR5-9600, PCI Express (PCIe) 6.0/5.0/CXL 3.2, Universal Chiplet Interconnect Express (UCIe)-SP 32G, and 10G multi-protocol PHY (USB3.x, DP-TX, PCIe 3.0, and SGMII) with companion controller IP. The SF5A platform includes LPDDR5X-8533 PHY IP for automotive applications, and the SF2P offering adds a 32G PCIe 5.0 PHY for AI/HPC needs.
Cadence’s digital full flow, including the Samsung Hyper Cell methodology and Local Layout Effect (LLE) timing accuracy, has been certified for the SF2P process node following a design and technology co-optimization (DTCO) project. The Cadence Pegasus Verification System is certified for SF2P and other Samsung nodes, with the physical verification flow optimized for signoff accuracy and scalability. Cadence and Samsung are also collaborating on DTCO for next-generation process nodes.
The companies have automated the migration of analog cell-based 4nm IP to the 2nm process node, maintaining functional and design intent to reduce turnaround time and development costs. Additionally, Cadence and Samsung demonstrated a Front-End Module (FEM)/Antenna-in-Package (AiP) co-design flow for mmWave applications on Samsung’s 14nm FinFET process, streamlining design data management across IC/module development stages.
For 3D-IC power integrity, Cadence and Samsung collaborated on a full-flow analysis using tools like Voltus InsightAI, Innovus Implementation System, and Integrity 3D-IC Platform. Applied to a high-speed CPU chip on Samsung’s SF2 node, Voltus InsightAI resolved 80-90% of IR-drop violations with minimal impact on timing and power.