AMD announced a significant milestone in high-performance computing with the successful tape-out and bring-up of its next-generation AMD EPYC processor, codenamed Venice, on TSMC’s advanced 2nm (N2) process technology. This achievement underscores the robust partnership between AMD and TSMC, highlighting their collaborative efforts to co-optimize new design architectures with cutting-edge process technology.
The Venice EPYC processor is the first HPC product in the industry to utilize TSMC’s N2 node, marking a major advancement in AMD’s data center CPU roadmap. The processor is on track for a launch next year, promising enhanced performance, power efficiency, and yields.
“TSMC has been a key partner for many years, and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing,” said Dr. Lisa Su, chair and CEO of AMD. “Being a lead HPC customer for TSMC’s N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing.”
In addition to the Venice processor, AMD also announced the successful bring-up and validation of its 5th Gen AMD EPYC CPU products at TSMC’s new fabrication facility in Arizona. This move underscores AMD’s commitment to U.S. manufacturing and its strategic efforts to diversify its supply chain.
“We are proud to have AMD as a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab,” said Dr. C.C. Wei, Chairman and CEO of TSMC. “By working together, we are driving significant technology scaling resulting in better performance, power efficiency, and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing.”
For more information, visit https://www.amd.com
