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S2C Showcases AI-Assisted RISC-V Verification and FPGA Prototyping at RISC-V Summit China

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S2C showcased RISC-V FPGA prototyping and AI-assisted debug workflows at RISC-V Summit China, including an Andes AX66 Linux KVM demonstration on its Prodigy S8-100 system. The design used 55% of the resources of a single AMD Versal Premium VP1902 FPGA. S2C said the demonstration showed the platform’s capacity for multicore 64-bit RISC-V IP prototyping and early software validation, including evaluation of edge AI inference workloads.

S2C also demonstrated RCF Agent using the open-source XiangShan RISC-V processor RTL. The agent initiates compilation, collects error messages and produces an initial analysis. Automating these steps can help engineers triage compile failures and reduce the effort required to get started on large RTL projects.

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S2C Showcases AI-Assisted RISC-V Verification and FPGA Prototyping at RISC-V Summit China

At the summit’s chip design and verification forum, S2C presented “LLM-based RISC-V Virtual Platform & Debug Flow.” The company said bring-up issues in increasingly complex RISC-V systems can span instruction execution, privilege modes, memory, interrupts, peripherals and software. Traditional debugging requires engineers to correlate logs, registers, memory dumps and disassembly manually, making investigations time-consuming and difficult to reproduce or hand off.

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The workflow combines a RISC-V virtual platform that models the processor, memory, buses, interrupt controller and common peripherals with an LLM-assisted layer for interpreting captured debug information. It can boot firmware, bootloaders and operating systems, and supports breakpoints, watchpoints, state inspection and execution tracing. Saving and restoring execution state helps teams reproduce failures, compare results and collaborate on root-cause analysis.

The sixth RISC-V Summit China was held Oct. 18–20 at the Shenzhen Convention and Exhibition Center (Futian). Following the presentation, attendees discussed how the workflow could fit into existing RISC-V development environments, including access to the virtual platform and support for custom ISA extensions. More information about S2C’s verification and prototyping solutions is available at www.s2cinc.com.

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EEHerald News Desk


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