DVCon India 2026 opened with a keynote vision talk by Dr. Prakash Narain, President and CEO of Real Intent, focused on transforming static sign-off through microarchitectural analysis and artificial intelligence.
Prakash defined static sign-off as a verification approach that relies on structural analysis to identify targeted bugs without requiring test cases or simulation. Long-established applications include static timing analysis, RC extraction, lint, clock-domain crossing (CDC), and reset-domain crossing (RDC). He noted that successful static sign-off solutions must deliver high capacity and accuracy, complete coverage of targeted issues, seamless integration into existing flows, and ease of use.
The effectiveness of static methods, he explained, stems from their deliberate targeting of specific problem classes. This focus enables predefined modeling of bugs, which in turn supports automation, technology abstraction for efficiency, and automated customization of reporting and debug.
Real Intent's technology has progressed from foundational structural analysis to techniques capable of handling greater complexity, culminating in microarchitectural analysis. The company's Conquest MAI solution identifies structural microarchitectural components within RTL designs and checks both their integrity and their usage in context. Illustrative checks include verification of FIFO controls (including reset behavior), analysis of state machines, detection of off-range counter values, and identification of unused states in components such as shifters. The use model is automatic and requires minimal additional setup.
Applied to CDC verification, microarchitectural analysis expands the traditional taxonomy to include additional structures such as counters and configuration elements, enabling more accurate isolation of interfaces. Prakash stated that this approach yields roughly 20 times better quality of results, or a 95 percent reduction in review effort.
A related application, Sentry, addresses design-for-security needs through automatic and command-driven checks focused on data confidentiality and related properties, aiming for scalable, standards-based coverage.
Prakash described AI as a practical paradigm, pointing to directions including knowledge agents that deliver information in natural language, generative capabilities for setup and configuration, and smart agents that assist with debug and proposed fixes. Together, microarchitectural analysis and AI form the core pillars of Real Intent's strategy for advancing applications and reducing verification effort.
Exclusive Interview Insights with EEHerald
In an exclusive interview with Srinivasa Reddy N - Editor of EEHerald at DVCon 2026, Prakash expanded on these themes.
He explained that designers think in terms of higher-level components rather than pure bit-level or Boolean (0/1/X) representations. Microarchitecture analysis extracts these inherent components — such as finite-state machines, FIFOs, counters, and shifters — from the structure of RTL. This higher-level view enables reasoning that is many times, or multiple orders of magnitude, more efficient than bit-level techniques. That information exists in RTL because it reflects how designers construct functionality; it cannot be recovered from a netlist, which loses structural form. Notably, the core technology requires no designer input or explicit intent annotations. Instead, it combines syntactic, semantic, structural, and Boolean analysis with targeted proof techniques to detect these standard functional components.
Asked about the cited 20x improvement in CDC violation report precision and the 95 percent reduction in designer review burden, Prakash noted that traditional CDC static sign-off tends to produce noisy results — users must review everything to sign off, and the sheer volume of information leads to mistakes. Existing tools largely operate at the bit level. With microarchitecture analysis, components built around clock-domain interfaces (such as FIFOs or handshake interfaces) are extracted and isolated, allowing precise verification of how crossings are constructed and delivering guaranteed results rather than noisy ones. He characterized the 20x improvement and the corresponding reduction to roughly 5 percent residual review burden as a current starting point, with the goal of continuing to close remaining gaps and improving further beyond 95 percent.
On the relationship between static sign-off and formal methods, Prakash observed that both are static but differ fundamentally. Formal methods aim for precise pass/fail outcomes but often run into analysis complexity and non-convergence, requiring expert guidance. Static sign-off, by contrast, relies on approximations: reported failures may be noisy and require user review or waiver, while passes are reliable. He added that microarchitecture analysis has the potential to benefit both domains, though Real Intent's focus remains on leveraging it within static applications rather than building formal tools.
Regarding scaling to chiplets and advanced interfaces, Prakash pointed out that while macro-architectures can vary widely, the underlying microarchitecture components — FSMs, FIFOs, and similar structures — remain more unified across platforms such as graphics or mobile designs. Staying at the microarchitecture level, he said, therefore supports the creation of generic applications that serve varied systems.
On the use of autonomous agents in static sign-off flows, Prakash emphasized that reliability is essential, comparing it to the need for reliable braking in a car. While AI continues to show promise, he said the technology has not yet reached the point of full confidence for broad autonomous use. Real Intent's initial focus is on applying agent techniques to improve debug — including suggestions for waivers and configurations — before advancing further.
Finally, addressing what static sign-off can and cannot cover, Prakash described semiconductor functional verification as requiring sign-off across a wide test plan of requirements. Static sign-off, he explained, provides customized applications for specific aspects of that plan, while simulation and formal methods serve as powerful generic tools that experts use to address other dimensions. Real Intent's roadmap is to expand the scope of static sign-off across more of the overall flow and increase efficiency, while recognizing that generic tools will continue to play complementary roles — much as static timing analysis and SPICE coexist in circuit analysis today.
Prakash closed by expressing strong enthusiasm for microarchitecture analysis, describing it, after several years of innovation, as a breakthrough whose current capabilities and future potential are especially promising.
Together, the vision talk and the interview underscored Real Intent's emphasis on practical, high-efficiency advances in static verification at DVCon India 2026.
Here is the video of the interview:
