Cadence launches industry-first DDR5 12.8Gbps MRDIMM Gen2 memory IP system solution for AI and Data centers

The Cadence DDR5 MRDIMM IP features a high-performance, scalable, and adaptable architecture based on Cadence’s proven DDR5 and GDDR6 product lines. With multiple engagements already underway with leading AI, HPC, and data center customers, this IP solution is demonstrating its early leadership in the market.

 

The DDR5 MRDIMM IP design has been validated in hardware using the latest MRDIMMs (Gen2), achieving a best-in-class 12.8Gbps data rate, effectively doubling the bandwidth of current DDR5 6400Mbps DRAM parts. This new IP offers a complete memory subsystem, including a PHY and a high-performance controller, based on Cadence’s silicon-proven architecture. It also features ultra-low latency encryption and industry-leading Reliability, Availability, and Serviceability capabilities.

 

“The Cadence DDR5 IP portfolio, combined with Micron’s industry-leading 1γ (1-gamma)-based DRAM, meets the growing demand for higher memory bandwidth, density, and reliability for AI processing workloads,” said Praveen Vaidyanathan, vice president and general manager of Micron’s Cloud Memory Product Solutions. “These memory enhancements are crucial for enabling the next generation of AI/ML and HPC applications in data center and enterprise environments.”

“Cadence’s DDR5 MRDIMM IP system solution, paired with MRDIMM modules featuring Montage’s memory buffers, delivers a high-performance memory subsystem for next-generation servers with doubled bandwidth,” said Stephen Tai, president at Montage Technology. “Montage’s MRCD02/MDB02 chips for MRDIMMs, capable of achieving 12.8Gbps data rates, are ready to enable server and data center products.”

Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence, added, “Data center and enterprise applications stand to gain a significant performance advantage from Cadence’s DDR5 12.8Gbps MRDIMM IP system solution. This new leading-edge memory IP system both raises the bar and establishes a roadmap that future-proofs our customers’ next-generation SoC and chiplet products for generations to come.”

Cadence’s DDR5 controller and PHY have been verified with Cadence’s Verification IP (VIP) for DDR to provide rapid IP and SoC verification closure. The Cadence VIP for DDR5 includes a complete solution from IP to system-level verification with DFI VIP, DDR5 memory model, and System Performance Analyzer.

For more information on the new solution, visit the https://www.cadence.com/