HBM4 standard released by JEDEC improving bandwidth, power efficiency, and capacity for AI and HPC

The advancements introduced by HBM4 are vital for applications that require efficient handling of large datasets and complex calculations, including generative AI,HPC, high-end graphics cards, and servers. HBM4 introduces numerous improvements to the prior version of the standard, including:
    Increased Bandwidth: With transfer speeds up to 8 Gb/s across a 2048-bit interface, HBM4 boosts total bandwidth up to 2 TB/s.

 

    Doubled Channels: HBM4 doubles the number of independent channels per stack, from 16 channels (HBM3) to 32 channels with 2 pseudo-channels per channel, providing designers with more flexibility and independent ways to access the cube.

 

    Power Efficiency: JESD270-4 supports vendor-specific VDDQ (0.7V, 0.75V, 0.8V, or 0.9V) and VDDC (1.0V or 1.05V) levels, resulting in lower power consumption and improved energy efficiency.

 

    Compatibility and Flexibility: The HBM4 interface definition ensures backwards compatibility with existing HBM3 controllers, allowing for seamless integration and flexibility in various applications.

 

    Directed Refresh Management (DRFM): HBM4 incorporates Directed Refresh Management for improved row-hammer mitigation and Reliability, Availability, and Serviceability (RAS).

 

    Capacity: HBM4 supports 4-high, 8-high, 12-high, and 16-high DRAM stack configurations with 24 Gb or 32 Gb die densities, providing for a higher cube density of 64GB (32 Gb 16-High).

“High performance computing platforms are evolving rapidly and require innovation in memory bandwidth and capacity,” said Barry Wagner, Director of Technical Marketing at NVIDIA and JEDEC HBM Subcommittee Chair. “Developed in collaboration with technology industry leaders, HBM4 is designed to drive a leap forward in efficient, high performance computing for AI and other accelerated applications.”

“JEDEC members are dedicated to developing the standards needed to support the technology of the future,” said Mian Quddus, Chairman of the JEDEC Board of Directors. He added, “The HBM Subcommittee’s efforts to continuously improve the HBM standard hold the potential to drive significant advancements in a wide variety of applications.”

Leading industry figures have praised the HBM4 standard for its significant advancements in memory technology. Joe Macri of AMD highlighted its critical role in AI, HPC, and graphics workloads. Boyd Phelps from Cadence emphasized its importance for AI hardware efficiency, while Nikhil Jayaram of Google Cloud noted its impact on next-generation training and inference systems. Meta's David Ramku, Micron's Praveen Vaidyanathan, Samsung's JS Choi, SK hynix's Jeff Choi, and Synopsys's Neeraj Paliwal all echoed the sentiment, recognizing HBM4's potential to drive innovation and meet the evolving demands of modern computing.

 

For more information, visit https://www.jedec.org.