Zero ASIC has unveiled world's first open-standard eFPGA IP product named Platypus addressing the issue of Obsolescence featuring:
100% open and standardized FPGA architectures
100% open source FPGA bitstream formats
100% open source FPGA development tools
Obsolescence Issue:
Obsolescence is a critical issue for FPGA-based systems within aerospace, defense, healthcare, communications, automotive, and industrial applications, where lifespans range from 10 to 50 years. For instance, consider the development of the F-35 fighter jet, which began in 1997 and didn’t enter full production until 2021. During this period, transistor density increased by a factor of 10,000X, and the FPGA industry introduced six new generations of architectures.This mismatch between the relentless pace of semiconductor advancements and slow infrastructure development cycles has led to an estimated $50B–$70B in obsolescence-related NRE costs for the US military with 15% of all replacement semiconductor parts being counterfeit.
Since the inception of FPGAs in the 1980s, commercial FPGA products have become increasingly complex, less standardized, and more opaque, exacerbating issues related to parts obsolescence and counterfeiting. In the best case, an end-of-life notice for an FPGA device or eFPGA IP core necessitates a complete subsystem redesign. In the worst case, it may result in the termination of an entire program.
The logical next step in addressing the FPGA obsolescence and counterfeit problems is to move away from single source parts and establish a set of open-standard FPGA architectures, similar to the successful standards created for memory and passive components.
Open FPGA History
There have been numerous attempts at opening up FPGAs over the last 25 years. The Versatile Place and Route (VPR) open source FPGA research platform was introduced in 1997 and has helped lower the barrier to high-quality, reproducible FPGA research ever since. Unfortunately, VPR has remained solely a research tool, and there is still no fully open RTL-to-bits flow for commercial FPGAs.
To address the lack of fully open FPGA devices, DARPA funded the OpenFPGAand PRGA FPGA generator research projects in 2018. While these open-source generators facilitated the tape-out of several academic chips, the resulting designs were neither standardized nor commercialized.
Taking a different approach to circumvent the issue of opaque FPGAs, numerous efforts have been made to reverse-engineer commercial FPGAs. However, as FPGA complexity has surged alongside Moore’s Law, this task has become increasingly difficult and costly.
Despite these valiant efforts, there is still not a single open and standardized commercial FPGA product in the market as of today
RISC-V and SFPGA have distinct characteristics. The architecture standard for RISC-V is the ISA specification, while for SFPGA, it is the FPGA architecture specification. Both can have open or closed hardware source codes. In terms of binary programs, RISC-V uses executables, whereas SFPGA uses bitstreams. Both architectures support binary compatibility. RISC-V is managed by the RISC-V International consortium, while the consortium for SFPGA is yet to be determined.
Andreas Olofsson, founder of Zero ASIC says “Developing an open-standard FPGA architecture and an ecosystem of standard compliant components will revolutionize FPGA-based system design, much like RISC-V has transformed CPU design. Just like with RISC-V, market dynamics will dicate whether the potential upside of open standards overcomes the status quo inertia of vendor lock-in.” .
Impact of Standardized FPGAs
The RISC-V ISA started as a humble UC Berkeley research project, with the first specification published in 2011. In 2014, David Patterson and Krste Asanovic made a compelling case for why ISAs should be free, igniting the RISC-V movement. A decade later, RISC-V is now shipping billions of devices annually.
Product Availability
Platypus standard eFPGA IP cores are available today to early access customers. For more information visit https://zeroasic.com/platypus.
