XCENA presented the architecture and measured performance of MX1, its computational CXL memory system, during the Memory session at Hot Chips 2026. The presentation, led by Harry Kim, XCENA's chief product officer, was selected through the Hot Chips program committee's technical review process, and examined how MX1 combines large-scale memory expansion, SSD-backed capacity, and programmable near-memory computing, meaning processing that happens physically close to where data is stored, into a single CXL Type 3 device aimed at addressing growing memory constraints in AI infrastructure.
The underlying challenge MX1 addresses is that as AI models continue growing, system performance is increasingly limited not just by raw compute power but by memory capacity, how efficiently data moves through the system, and the economics of scaling high-bandwidth memory. MX1 is designed to complement CPUs, GPUs, and AI accelerators by expanding available memory capacity and offloading certain memory-intensive operations, including vector search, KV-cache retrieval (accessing cached intermediate data used during AI inference), and data preprocessing, so that host processors can stay focused on the more compute-intensive parts of running AI inference.
MX1 combines three architectural capabilities into a single CXL Type 3 device. First is memory expansion, offering up to 2TB of DDR5 memory across four memory channels, connected using CXL 3.2 running over a PCIe 6.0 interface. Second is SSD-backed capacity, delivered through XCENA's InfiniteMemory technology, which exposes SSD storage through a byte-addressable CXL memory interface while transparently caching frequently accessed 64KB data pages in faster DRAM memory. Third is near-memory computing, using more than 1,000 custom RISC-V processor cores organized into what XCENA calls Memory Acceleration Units, which execute highly parallel, memory-intensive workloads close to where the data actually sits. Integrated vector processing engines provide roughly 3 TFLOPS of FP32/FP16 dot-product throughput, supporting workloads like vector search and KV-cache scoring.
Kim said Hot Chips is where the industry evaluates new computing architectures based on their technical merit, and that the presentation shared MX1's architectural design, software model, and measured performance, demonstrating how computational CXL memory can help address the growing capacity and data-movement challenges facing AI infrastructure.
XCENA evaluated MX1's performance across six representative data-processing tasks commonly found in analytics and AI pipelines: compression, decompression, Parquet decoding (a common data file format used in analytics), less-than filtering, LIKE filtering (a type of text-matching query), and aggregation. Compared to a host CPU processing data over a standard CXL connection, a single MX1 delivered up to 4.7 times higher throughput and 18.7 times greater energy efficiency. Compared to the same host CPU processing data from its own local DDR5 memory, MX1 delivered up to 2.0 times higher throughput and 6.2 times greater energy efficiency.
Kim said these results demonstrate the value of running highly parallel, memory-bound workloads closer to where the data actually resides, and that MX1 is designed to complement the host processor by reducing unnecessary data movement, freeing up CPU resources to focus on operating system tasks, orchestration, and general-purpose computing.
On the software side, developers can program MX1 using standard C/C++ or Rust through XCENA's LLVM-based software toolchain. The company's PXL runtime schedules and synchronizes workloads across the device's RISC-V processing cores while providing a shared virtual address space, simplifying memory management for complex data structures and running multiple applications at once. At a higher level, XCENA's XFLARE analytics library integrates with SQL database engines and FAISS-based vector search systems, and the broader software stack is being extended to support widely used AI and data frameworks including Apache Arrow, PyTorch, and vector databases, with more SDK integrations planned over time.
XCENA plans to begin mass production of MX1 by the end of 2026, with initial customer revenue targeted for 2027.
