proteanTecs, a provider of deep data visibility technology for advanced electronics, has introduced a dedicated suite of health, power, and performance management solutions for multi-die systems, meaning chips built by combining multiple smaller dies, or chiplets, into a single package. Built on the company's own on-chip monitoring technology, the new solutions are meant to help semiconductor and system companies improve manufacturing yield, reduce risk, and protect their investments in high-value systems-in-package (SiP), a packaging approach that combines multiple chip components into one integrated unit.
Evelyn Landman, co-founder and CTO of proteanTecs, said deep, per-chiplet visibility lets customers understand not just whether a complex system-in-package works overall, but how each individual die is behaving and how the different dies interact with one another.
The move reflects a broader shift happening in chip design driven by AI: as processors, accelerators, memory, and connectivity components are increasingly combined into sophisticated multi-die packages, managing each component in isolation is no longer sufficient. Building on its existing deep data analytics and real-time power, performance, and reliability tools, proteanTecs is expanding its offering with capabilities specifically designed for chiplet-based architectures. These combine what the company calls shift-left chiplet quality assurance, meaning catching quality issues earlier in the development process, correlation between pre- and post-packaging data, synchronized analysis across multiple chiplets, and analysis spanning multiple data streams. Together, these capabilities provide visibility into individual chiplets and reveal effects that only emerge once components are integrated together, such as thermal gradients, power and clock noise, structural stress, and behavior that varies depending on the workload being run. These monitoring capabilities extend into live operation as well, providing ongoing awareness of thermal conditions, power use, and timing margins to support real-time optimization of power, performance, and reliability once a system is deployed in the field.
As the system-in-package increasingly functions as a complex system in its own right rather than just a collection of parts, proteanTecs frames its offering as letting customers move beyond monitoring individual components in isolation to understanding how chiplets behave and interact as part of the full assembled package.
With advanced packaging, the cost of discovering a marginally defective die rises sharply once that die has already been integrated with other expensive components. proteanTecs argues that being able to identify risk earlier, by reducing defective parts per million (DPPM) beyond current best-known testing methods at the wafer-sort stage, understanding what changes during package assembly, and making better decisions at each step, can meaningfully affect overall compound yield, quality, and the economics of the finished system. The company says this helps customers increase confidence in known-good-die and known-good-stack quality, improve compound yield across multi-die architectures, gain better visibility into packaging and power delivery quality, reduce development risk and speed up time-to-market, optimize power and performance in constrained multi-die systems, and improve long-term reliability over a system's lifecycle.
Landman said advanced packaging introduces subtle electrical, thermal, and mechanical interactions that conventional pass-or-fail testing simply can't reveal, and that deep, per-chiplet visibility lets customers understand not just whether a complex system-in-package works, but how each die behaves and interacts with others, from initial production through years of use in the field.
proteanTecs says it's already scaling these advanced packaging capabilities through multi-year, multi-generation partnerships with major customers, building on its existing experience delivering deep data analytics and real-time reliability, power, and performance optimization across chips and broader systems.
To explore the challenges and opportunities around advanced packaging further, proteanTecs will host a webinar with Amkor Technology titled "Advanced Packaging at Scale: Power, Performance, and Reliability in the Chiplet Era" on August 26, 2026, at 10:00 a.m. PDT. Nir Sever, senior director of business development at proteanTecs, and Vineet Pancholi, senior director and manufacturing test technologist at Amkor, will discuss approaches to addressing power, performance, and reliability as chiplet-based designs move toward large-scale production.
