VLSI
Arasan Unveils Total IP Solution for Embedded USB2 with Controller and PHY for Mobile and Automotive SoCs
Arasan Chip Systems, a provider of semiconductor IP for mobile and automotive System-on-Chips (SoCs), announced the immediate availability of its Embedded USB2 (eUSB2) IP Core, including the eUSB v2 Controller and eUSB v2 PHY IP. The eUSB2 IP is designed for SoCs operating at a 1.2V interface vol
2 min read
Cadence Unveils LPDDR6/5X 14.4Gbps Memory IP to Support AI and HPC Infrastructure
Cadence announced the tapeout of an LPDDR6/5X memory IP system solution operating at 14.4Gbps, achieving up to 50% higher speed than the previous LPDDR generation. The solution is designed to meet the memory bandwidth and capacity needs of AI large language models, agentic AI, and compute-intensi
3 min read
RISC-V Multi-Core and Many-Core Architectures-part2
RISC-V Multi-Core and Many-Core Architectures -Continued Many-Core RISC-V ArchitecturesScaling to Many-Core Systems
47 min read
RISC-V Multi-Core and Many-Core Architectures
The open-source RISC-V instruction-set architecture has moved from academic curiosity to mainstream technology in barely a decade, shipping more than 10 billion cores by 2022 and expanding at a pace that outstrips earlier ISAs such as x86 and ARM. Market analysts forecast an add
65 min read
AI-Powered Questa One at Siemens U2U EDA Verification Forum Focuses on Making DV Engineer Smarter
At the Siemens EDA Users2Users Verification Forum 2025 held in Bangalore on 3rd July 2025, Siemens EDA showcased its AI based advancements in VLSI design and verification, with a spotlight on its AI-powered Questa One platform. The event, attended by industry leaders and verification engineers, h
4 min read
Ruchir Dixit’s Cricket Analogy Inspires Teamwork in VLSI Chip Verification at Siemens EDA Forum
At the Siemens EDA Users2Users Verification Forum 2025 in Bangalore, Ruchir Dixit, Vice President and Country Manager of Siemens EDA, opened with a compelling cricket trophy winning analogy, drawing parallels between Royal Challengers Bengaluru’s (RCB) 2025 IPL victory and the teamwork esse
5 min read
Strategic Opportunities and Challenges in Semiconductor IP Development Using Gen AI LLMs
The semiconductor silicon intellectual property (IP) market plays a pivotal role in the semiconductor industry by providing reusable design components, known as IP cores, for integrated circuits (ICs) and semiconductor chips. These pre-designed and verified blocks, including processors, memory co
7 min read
VLSI Design: LVS (Layout Versus Schematic) in OpenROAD Environment -p3
Continued from VLSI Design: LVS (Layout Versus Schematic) in OpenROAD Environment -p2 LVS Script Development Basic LVS Script Structure
30 min read
Understanding RISC-V architecture: A detailed guide to the open-source ISA revolution- P3
Continued from Understanding RISC-V architecture: A detailed guide to the open-source ISA revolution- P2 Design
19 min read
Understanding RISC-V architecture: A detailed guide to the open-source ISA revolution- P2
Continued from
61 min read
Understanding RISC-V architecture: A detailed guide to the open-source ISA revolution
For decades, the landscape of general-purpose and embedded computing has been dominated by two proprietary instruction set architectures: Intel’s x86 and Arm’s RISC-based architecture. Th
65 min read
VLSI Design: LVS (Layout Versus Schematic) in OpenROAD Environment -p2
Continued from VLSI Design: LVS (Layout Versus Schematic) in OpenROAD Environment OpenROAD Architecture <
63 min read
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