Cadence Unveils LPDDR6/5X 14.4Gbps Memory IP to Support AI and HPC Infrastructure

Cadence announced the tapeout of an LPDDR6/5X memory IP system solution operating at 14.4Gbps, achieving up to 50% higher speed than the previous LPDDR generation. The solution is designed to meet the memory bandwidth and capacity needs of AI large language models, agentic AI, and compute-intensive workloads across AI, high-performance computing (HPC), and data center applications. Multiple customer engagements are underway with AI, HPC, and data center clients.

The Cadence LPDDR6/5X IP includes a PHY architecture and a high-performance controller supporting both LPDDR6 and LPDDR5X DRAM protocols, including LPDDR5X CAMM2, for flexibility in traditional monolithic SoCs and multi-die system architectures. It leverages Cadence’s chiplet framework for heterogeneous chiplet integration, with prior LPDDR generation chiplet designs taped out in 2024. The solution is built on Cadence’s DDR5 12.8Gbps, LPDDR5X 10.7Gbps, and GDDR7-36G product lines, focusing on power, performance, and area optimization.

The LPDDR6/5X PHY is customizable for various package and system topologies and available as a hardened macro for reliable integration. The controller, provided as a soft RTL macro, supports the Arm AMBA AXI bus and offers flexibi...