JEDEC Solid State Technology Association announced milestones from its JC-40 and JC-45 Committees for Logic and DRAM Modules. The updates include the publication of a new DDR5 multiplexed rank data buffer (MDB) standard, progress on a multiplexed rank registering clock driver (MRCD) standard, and ongoing work on the DDR5 multiplexed rank DIMM (MRDIMM) Gen2 roadmap.
Published:JESD82-552 (DDR5MDB02) Multiplexed Rank Data Buffer. The standard defines next-generation data buffer functionality for multiplexed rank DIMM architectures to support robust operation as module bandwidth scales.
Expected soon:JESD82-542 (DDR5MRCD02) Multiplexed Rank Registering Clock Driver. This standard is intended to strengthen signal integrity and timing control in DDR5 MRDIMM module designs.
In progress: The JC-45 Committee is nearing completion of the MRDIMM Gen2 standard.
In development: Gen2 DDR5 MRDIMM raw card designs targeting 12,800 MT/s, and development of the MRDIMM Gen3 module standard, with underlying memory interface logic nearing finalization.
These efforts enable higher bandwidth scaling for DDR5 MRDIMM designs.
“These coordinated efforts in JC-45 reflect JEDEC’s ongoing role in aligning the industry around interoperable, high-performance memory standards that meet the growing demands of AI, cloud computing, and enterprise workloads,” said Mian Quddus, Chairman of the JC-45 Committee and the JEDEC Board of Directors.
JEDEC standards are subject to change during and after the development process, including disapproval by the JEDEC Board of Directors.
