Silvaco Group announced the immediate availability of the Mixel MIPI "Production Ready Offerings," referred to as Mixel MIPI PRO IP. Silvaco, a provider of AI-enabled TCAD, EDA, and SIP solutions for semiconductor design and digital twin modeling, stated that this expands its silicon IP offerings.
The portfolio includes MIPI PHY IP for MIPI D-PHY, MIPI C-PHY, and MIPI M-PHY, along with multi-standard SerDes IP such as MIPI C-PHY/D-PHY combo IP and LVDS/D-PHY combo IP. Mixel announced support for the Automotive SerDes Alliance (ASA) Motion Link IP in 2025. These solutions target markets including mobile, automotive, virtual reality (VR), augmented reality (AR), Internet of Things (IoT), wearables, and sensors.
Mixel's MIPI PHY IP is silicon-proven in multiple MIPI-compliant configurations, including the patented MIPI D-PHY RX+ topology. This implementation supports full-speed production testing without a full D-PHY Universal configuration, reducing area by 35% and leakage power by 50%. The solution was first announced in 2015 and is in production at several large semiconductor and system companies for mission-critical applications.
Mixel was the first pure-play silicon IP provider to announce ASA Motion Link SerDes IP availability in 2025. The Automotive SerDes Alliance standardizes long-reach, asymmetric SerDes connectivity for automotive use.
The Mixel IP is silicon-proven across 9 foundries and 12 process nodes, ranging from 180nm to 5nm.
The MIPI PHY offerings include:
- MIPI D-PHY IP v3.5 (backwards compatible), supporting 1–4 data lanes at up to 6.5Gbps per lane, for MIPI CSI-2 and MIPI DSI/DSI-2, available in TX, RX, TX+, RX+, and Universal implementations.
- MIPI C-PHY IP v2.1 (backwards compatible), supporting 1-3 trios at up to 8.0Gsps per trio (18.24Gbps), for MIPI CSI-2 and MIPI DSI/DSI-2, available in TX, RX, TX+, RX+, and Universal implementations.
- MIPI M-PHY IP v4.1 (backwards compatible), supporting HS-G1 to HS-G4 at up to 11.6Gbps, for MIPI UniPro and JEDEC UFS standards.
Multi-standard SerDes includes:
- MIPI C-PHY/D-PHY Combo IP, supporting v2.1 and v3.5, with 4 lanes/3 trios at up to 8.0Gsps/trio and 6.5Gbps/lane, for MIPI CSI-2 and MIPI DSI/DSI-2, available in TX, RX, TX+, RX+, and Universal implementations.
- MIPI D-PHY/LVDS Combo IP, supporting MIPI D-PHY and LVDS (TIA/EIA-644 compatible), available as TX and RX.
Automotive SerDes includes:
- ASA Motion Link SerDes IP, supporting v2.1, with TX and RX downstream speeds up to 8.0Gbps per lane using NRZ signaling (Speed Grade 3).
Andy Wright, Senior Vice President and General Manager of Silvaco's Semiconductor IP Business Unit, stated that Mixel's 27-year history of first-time silicon success, combined with Silvaco's global reach, provides partners with proven solutions for interconnect challenges.
The announcement follows Silvaco's acquisition of Mixel Group, Inc., completed in August 2025, which integrated Mixel into Silvaco's Semiconductor IP Business Unit. This move expands coverage at advanced process nodes and supports high-growth applications, with focus on quality, reliability, and customer support.
