Alphawave Semi tapes out UCIe IP subsystem on TSMC’s 2nm process

Alphawave Semi announced the tape out of a UCIe IP subsystem on TSMC’s 2nm process, supporting 36G die-to-die data rates. The subsystem is integrated with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) packaging technology, achieving a bandwidth density of 11.8 Tbps/mm. This development supports scalable chiplet architectures for AI and high-performance computing (HPC) workloads.
The UCIe IP subsystem complies with the UCIe 2.0 standard and supports multiple protocols, including PCIe, CXL, AXI, and CHI, using Alphawave Semi’s Streaming Protocol D2D Controller. It includes features such as per-lane health monitoring and testability, with low power and latency. The tape-out follows the release of Alphawave Semi’s AI Platform, aimed at supporting disaggregated System-on-Chips (SoCs) for hyperscale AI and HPC infrastructure.
Mohit Gupta, Senior VP & GM of Custom Silicon & IP at Alphawave Semi, stated that the 36G subsystem supports high-density, power-efficient chiplet connectivity and sets the stage for future 64G UCIe solutions. Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC, noted that the collaboration with Alphawave Semi leverages TSMC’s process and packaging technologies to meet AI and cloud infrastructure demands through the Open Innovation Platform.
Alphawave Semi is working on next-generation UCIe solutions, including 64G UCIe support, to address evolving chiplet-based AI and HPC applications.