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Accellera announces free access to IEEE Standard 1801 UPF 4.0 for low power design via IEEE GET program

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Accellera announces the newly published IEEE Standard 1801-2024 Unified Power Format  4.0 is now available for free download through the IEEE GET Program.
“Our collaboration with the IEEE Standards Association empowers design and verification engineers worldwide with fee-free access to leading-edge standards,” stated Lu Dai, Accellera Chair. “By providing IEEE Standard 1801 through the GET Program, we offer designers a valuable resource to explore, craft, verify, and apply power-aware concepts to electronic systems and deliver power-aware silicon IP. This accelerates learning and adoption, fostering a global community with a shared foundation of knowledge and best practices.”

IEEE Standard 1801, also known as UPF, is a standardized specification language designed to define the low-power architecture of an ASIC. It streamlines integration throughout the entire verification and implementation process. Built on Tool Command Language, UPF complements existing hardware description languages such as SystemVerilog and VHDL. It allows designers to specify essential power management elements such as power domains, supply networks, power shutoff, and multi-voltage designs.

The IEEE Standard 1801-2024 version introduces several significant innovations to keep pace with the rapidly evolving low-power design and verification methodologies. Innovations such as supply net tunneling and Value Conversion Method create new interfaces between analog/mixed-signal and the digital design spaces. Major extensions to the retention specification enable precise modeling of the most advanced state retention cells.

Additionally, the introduction of refinable macros supports new IP methodologies, allowing in-context optimizations while preserving IP verification efforts. Overall, this revision includes over 65 topics implemented by the working group, representing a broad spectrum of productivity, verification, and low-power design enhancements that will benefit the low-power design community.

Other key new features to the standard include:
Virtual supply and supply sets
Improved successive refinement methodology with implementation UPF
Clarification of precedence rules
Updates on object naming, especially escape and generate block names
Introduction of abstract power source
UPF library

For a list of Accellera standards and Accellera-sponsored IEEE standards available for download at no cost, visit the Accellera Download Page


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