IBM and Siemens have announced research to advance IBM’s nanostack architecture, a transistor design the companies are working to prepare for manufacturing and production at scale.
IBM demonstrated the viability of the architecture earlier this year. Additional advances are needed to prepare the technology for manufacturing and production at scale.
Nanostack is described as a three-dimensional, nanosheet-based design that vertically stacks and staggers transistors to pack more transistors onto a chip. At its current 7 angstrom node, it has nearly 100 billion transistors in a space the size of a fingernail. The design also allows different material combinations within each stacked layer to optimize the performance and power efficiency of each transistor independently.
The collaboration will focus on design, simulation and lithography techniques for current and future nanostack generations beyond the 7 angstrom node. IBM and Siemens will develop advanced virtual models to model performance, optimize designs and address fabrication challenges before chips are built.
Huiming Bu, vice president of Silicon Technology R&D at IBM, said: “Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D, representing a new paradigm for the semiconductor industry and a path forward for the logic scaling needed to support AI and other emerging technologies over the coming decade.”
The companies aim to accelerate technology development cycles and advance the manufacturing foundation needed to bring nanostack toward production.
