Processors

Lattice Mach-N2 family enhances secure control FPGA leadership

Listen to this story

AI NARRATED
0:00 / 0:00

Lattice Semiconductor has rolled out a new FPGA lineup, Mach-N2, aimed at reinforcing its foothold in secure control chips for infrastructure systems. Built on the company's Nexus 2 small-FPGA platform, the devices pair on-chip flash storage and a hardware root of trust with post-quantum cryptography that meets CNSA 2.0 standards  and they're designed so those cryptographic algorithms can be updated later as security needs evolve.

Esam Elashmawi, the company's Chief Strategy and Marketing Officer, tied the launch to mounting pressure from post-quantum mandates, noting that customers building infrastructure meant to last for years want chips that can handle both today's and tomorrow's security demands. He described Mach-N2 as a meaningful jump in logic density and bandwidth, paired with what he called the most complete post-quantum security package available in its class for long-lifecycle systems.

On performance, the new chips offer up to twice the logic density of earlier generations for control tasks, improved high-speed data connections for linking to modern processors and system-on-chip designs, and low-latency, real-time monitoring  useful for power sequencing and system management across computing, communications, and industrial equipment.

Security is a major focus: the devices support a full post-quantum cryptographic suite (ML-DSA, LMS, and XMSS for authentication, ML-KEM for key exchange) compliant with CNSA 2.0, plus the ability to swap in new algorithms in the field and protections against rollback attacks. They also use physically unclonable functions to establish unique device identities, support attestation protocols for verifying supply-chain and platform integrity, offer standard encryption options like AES-256, 521-bit ECC, and 4096-bit RSA, and include configurable tamper-detection features.

The chips also integrate non-volatile flash memory directly on-die, which blocks outside access to configuration data, and they boot unusually fast  a 220,000-logic-cell device can fully configure itself in under 30 milliseconds. Up to three separate configuration images can be stored for backup and recovery purposes. Connectivity options include PCIe 4.0, 10G Ethernet, and SERDES links running up to 16 Gbps.

ADVERTISEMENT
Advertisement
E

EEHerald News Desk

Editor, Electronics Engineering Herald


More from Processors