DVCon India 2026 will take place from September 1-3, 2026, at Radisson Blu in Marathahalli, Bengaluru. The conference addresses the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. EEHerald is the official media partner for this event. If you closely follow VLSI design trends or want to keep learning, check our website for comprehensive pre- and post-event coverage.
The event extends to three full days to allow additional time for papers, discussions and coverage of topics including AI-driven methodologies, system-level design, hardware-software co-verification and emerging standards. Shreya Dasgupta of Analog Devices who serves as General Chair has said "As General Chair, I am thrilled to invite you to join us for what promises to be our most expansive event yet. Building on the success of previous DVCon editions, we are excited to extend the program to three full days—inspired by the robust agendas of previous years. This allows even more time for papers, discussions and deep dives into cutting-edge topics in design and verification, including AI-driven methodologies, system-level design, hardware-software co-verification, and emerging standards. We are in the final stages of securing IEEE technical sponsorship, underscoring the conference’s commitment to high-quality, peer-reviewed technical content that advances our industry. DVCon India 2026 is your platform to connect, collaborate, and contribute."
Day 1 includes:
- Vision Talk by Real Intent: “Transforming Static Sign-Off with Microarchitectural Analysis & AI,” presented by Dr. Prakash Narain, President & CEO. The talk covers a two-pillar approach using generative and agentic AI to accelerate sign-off workflows, along with Microarchitecture Analysis technology to infer standard functional components such as FSMs, FIFOs, multi-port RAMs, stacks, counters and shifters. This supports early microarchitectural integrity verification and can produce more precise clock domain crossing violation reports.
- Keynote Talk by NXP: “Engineering at the Speed of Thought: AI-Driven Acceleration for the next gen designs,” with presenter Hitesh Garg, Vice President and India Managing Director of NXP Semiconductors.
- Keynote Talk by Elinnos: “Beyond Simulator + AI: AI-Integrated Simulation for Intelligent Verification.”
Day 2 includes:
- Vision Talk by Siemens: “The Future of Verification: One Path to Silicon Confidence,” presented by Abhi Kolpekwar, Senior VP & GM – Digital Verification Technologies, Siemens EDA. The presentation examines verification amid software-defined products, multi-die integration, safety and security requirements, power constraints and AI-driven workloads, and discusses a model that unifies intent, data, engines and people across the lifecycle while using AI to reduce coordination overhead.
- Keynote Talk by Synopsys: “Generative AI: Is it Real or Merely a Hallucination?” presented by Pallab Dasgupta, Vice President of R&D Engineering, Synopsys. The session reviews the current state of generative AI in design and verification, Synopsys investments in agentic solutions, and technology implemented in production environments.
- Keynote Talk by Cadence: “Agentic AI for Chip Design: Evolving from Coding Assistants to Super Agents,” presented by Ziyad Hanna, Corporate VP, R&D, Cadence Design Systems. It addresses up-leveling AI solutions through agentic orchestration, multi-agent approaches, EDA harnesses for iterative workflows and integration with tools and engines.
- Keynote Talk by Analog Devices: “Physical Intelligence Needs a New Engineering Stack: Rethinking Architecture and Execution for Intelligent Physical Systems,” presented by Anil Kempanna, VP, Global Head of Digital Hardware Design. The talk covers convergence of architecture, hardware, software, AI models, verification and execution for intelligent physical systems.
- Industry Panel: “Startup resurgence - Why it's a break out point for India.”
Day 3 includes:
- Vision Talk by Axiomise: “Proof, Not Prompt: Why AI Silicon Needs Formal Verification, Not Just AI-Generated Assertions,” presented by Ashish Darbari, Founder & CEO. The presentation addresses verification challenges in AI accelerator chips involving mixed-precision datapaths, tensor cores, MAC arrays, HBM memory controllers, network-on-chip fabrics and UCIe links. It notes first-time-right silicon at 14 percent and discusses formal verification for issues such as silent data corruption, deadlock-inducing NoC bugs and BF16 divider underflow. The talk covers combining AI-generated assertions with rigorous proof engineering, state-space explosion, inconclusive results and skills barriers, along with domain-centric apps in the axiomiser platform that have achieved more than 99 percent exhaustive proofs on large NoCs and RISC-V processors.
- Industry Panel: “From Classroom to Chip Design: Preparing the Workforce for the Semiconductor-AI Era.” Moderator: Ramanujam Thodur (Texas Instruments). Panelists: Ameya Pangarkar (Astera Labs), Sreenu Yerabolu (Lancesoft), Priya Ananthakrishnan (Mirafra).
- Industry Talk by Prodigy Technovations: “Bridging Pre-Silicon Verification to Post-Silicon Debug with Protocol-Aware Tools,” presented by Vibhav Kaki, Sr. Software Engineering Manager. The session covers protocol-aware tools for protocol decode, analysis, traffic generation, error injection and validation across simulation and real silicon, supporting technologies including I3C, UFS, PCIe, eMMC, SD, SPMI, RFFE, xSPI, QSPI, SPI, I2C and UART, for use cases from early verification to silicon bring-up, compliance, interoperability, system-level debug, emulation, prototyping and post-silicon validation.
Registration is open. Here is the link: https://dvcon.expoplato.com/events
