Arteris, announced a collaboration with MIPS, a GlobalFoundries company, to accelerate development of physical AI computing platforms. MIPS has selected Arteris FlexGen smart NoC IP and Magillem SoC integration automation software for its platforms. The collaboration targets high-growth markets including automotive microcontroller units (MCUs), advanced driver assistance systems (ADAS), robotics, and embedded computing using MIPS RISC-V processors.
The partnership addresses data movement bottlenecks, physical design challenges, and time-to-market pressures in domain-specific silicon for physical and edge AI applications. MIPS will integrate Arteris system IP into its platform offerings to enable optimized SoCs.
The collaboration builds on a 2024 partnership focused on high-performance RISC-V SoCs. MIPS is using Arteris FlexGen smart NoC IP, Magillem Connectivity, and Magillem Registers SoC integration automation software to accelerate platform design and iterations for high performance, energy efficiency, and solution delivery.
“We are focused on delivering high-performance, scalable compute platforms that enable our customers to deliver innovation in their next-generation physical AI platforms. By integrating Arteris technology into our design capabilities and platform offerings, we can accelerate custom silicon development, unlock system architecture optimizations, and deliver a flexible foundation to our customers,” said Sameer Wasson, CEO of MIPS.
“Modern SoCs and sophisticated MCUs are increasingly defined by processor capabilities and efficient data movement, especially in physical AI systems,” said K. Charles Janac, president and CEO of Arteris. “MIPS adoption of Arteris technology as a provider for data movement in custom silicon for physical AI reflects the growing need for fast, physically aware NoC architecture and scalable platform development. Together, we are enabling a new generation of efficient, high-performance physical AI platforms and helping customers accelerate innovation.”
Arteris enables AI data movement in chiplets, SoCs, and MCUs based on Arm, RISC-V, and x86 architectures.
