Navitas Semiconductor announced the addition of two new packages to its 5th generation GeneSiC technology platform: a top-side cooled QDPAK and a low-profile TO-247-4L with asymmetrical leads. The devices are 1200 V SiC MOSFETs based on the latest Trench-Assisted Planar (TAP) technology.
The 5th generation Trench-Assisted Planar technology provides a 35% improvement in RDS,ON × QGD figure of merit compared to the previous generation and about a 25% improvement in QGD / QGS ratio. It includes a stable high threshold voltage VGS,TH of more than 3 V, which provides immunity against parasitic turn-on for robust and predictable switching performance.
The top-side cooled QDPAK package enables heat dissipation directly through the top of the package to the heatsink, addressing thermal limitations of conventional PCB cooling. This design improves heat dissipation efficiency and supports smaller system footprints. It minimizes parasitic inductance for cleaner switching and higher efficiency at high frequencies. The package accommodates larger die sizes and higher current capability, supporting low RDS(ON) values in high-power applications, and features a compact surface-mount profile for high-volume automated assembly.
QDPAK specifications include:
Compact footprint of 15 mm x 21 mm with a height of 2.3 mm.
Enhanced creepage distance of 5 mm achieved via a groove in the package mold compound, without reducing the exposed top-side thermal pad area.
Support for up to 1000 VRMS applications with an epoxy molding compound having a Comparative Tracking Index greater than 600.
Design for easier system-level thermal integration via top-side cooling.
The low-profile TO-247-4-LP is a through-hole package variant optimized for systems with limited vertical clearance, such as high-density AI power racks. It reduces package height on the PCBA compared to a standard TO-247-4, enabling higher power density. It includes asymmetrical leads (thin leads for gate and Kelvin-source) to improve manufacturing tolerances on the PCBA. The package targets applications like AI data center power supplies where form-factor and height constraints apply.
Initial products announced include:
G5R06MT12QP: QDPAK, 1200 V, RDS,ON 6.5 mΩ
G5R12MT12QP: QDPAK, 1200 V, RDS,ON 12 mΩ
G5R06MT12LK: TO-247-4-LP, 1200 V, RDS,ON 6.5 mΩ
G5R12MT12LK: TO-247-4-LP, 1200 V, RDS,ON 12 mΩ
Paul Wheeler, VP & GM of the SiC business unit at Navitas, stated that the new packages address customer requirements for more power in less space in AI data center and energy infrastructure applications.
A white paper on the Trench-Assisted Planar technology is available for free download from the Navitas website.
Navitas uses the term ‘AEC-Plus’ to indicate parts exceeding AEC-Q101 and JEDEC standards for reliability testing based on its test results.
