Cadence announced the launch of the ChipStack AI Super Agent, an agentic AI solution for front-end silicon design and verification. The company describes the ChipStack AI Super Agent as the world’s first agentic workflow for automating chip design and verification. It autonomously creates and verifies designs from specifications and high-level descriptions. The solution provides up to 10X productivity improvements in coding designs and testbenches, creating test plans, orchestrating regression testing, debugging, and automatically fixing issues.
Anirudh Devgan, president and CEO of Cadence, stated that ChipStack advances the company’s design-for-AI and AI-for-design strategy by applying agentic AI to customers’ front-end flows to address the complexity and scale of modern chips. He noted that intelligent agents autonomously call underlying tools, enabling productivity gains in design and verification tasks while allowing engineering talent to focus on innovation.
The ChipStack AI Super Agent fits within Cadence’s Intelligent System Design approach, combining AI orchestration, principled simulation, and accelerated computing. It orchestrates multiple virtual engineers using Cadence’s foundational EDA tools and integrates with existing Cadence optimization AI and AI assistant solutions, including the Verisium Verification Platform, Cadence Cerebrus Intelligent Chip Explorer, and the JedAI data and AI platform. These solutions have been used in over 1,000 tapeouts to date.
The agent supports cloud-based and on-premises frontier models, including open NVIDIA Nemotron models customizable with NVIDIA NeMo, as well as cloud-hosted models such as OpenAI GPT.
Paul Cunningham, vice president and general manager of Research and Development at Cadence, said customers face a shortage of senior engineering talent for product roadmaps. He described the ChipStack AI Super Agent as addressing design and verification productivity, with deployments ramping quickly.
The ChipStack AI Super Agent is in early deployment with companies including Altera, NVIDIA, Qualcomm, and Tenstorrent.
Arvind Vidyarthi, senior director of engineering at Altera, stated that the agent reduced verification effort by approximately 10X in some areas, enabling faster and more confident closure. He noted that combining an interactive engineer-in-the-loop experience with Cadence’s AI-driven verification technologies delivers productivity gains and deeper functional coverage on complex designs.
Timothy Costa, GM of Industrial and Computational Engineering at NVIDIA, said semiconductor complexity requires AI for next-generation chips. He highlighted the collaboration with Cadence, including the ChipStack AI Super Agent, as combining intelligent reasoning capabilities like Mental Models and automated formal test plan generation with NVIDIA accelerated computing to improve productivity and efficiency.
Paul Penzes, vice president of engineering at Qualcomm, said the company is collaborating with Cadence on evaluating the ChipStack AI Super Agent for a broad user base. Early results show strong performance enhancements, with expectations for productivity gains.
Daniel Cummings, principal engineer of RISC-V Cores at Tenstorrent, stated that ChipStack improved formal verification efficiency. In a three-month evaluation on three critical design blocks, it reduced verification time by up to 4X. Running the agent on Tenstorrent hardware demonstrated high-performance on-prem inference for production-scale LLM workloads.
The Cadence ChipStack AI Super Agent is available now in early access. Additional information is available on Cadence’s AI for Design product page.
