Creonic GmbH announced an updated version of its SDA OCT IP Core, designed for Optical Communications Terminal implementations standardized by the Space Development Agency (SDA). The release includes architectural improvements intended to simplify system integration for both current and future OCT deployments. Key changes in the updated IP core include operation in a single clock domain, which reduces design complexity and facilitates integration into FPGA-based systems.
The core now features flexible frame synchronization with configurable parameters, allowing adaptation to different link configurations and system requirements. It incorporates timestamp passthrough functionality to enable precise time alignment, while deliberately excluding internal timestamp synchronization logic to avoid imposing constraints on system-level timing approaches.
Resource utilization has been optimized to support efficient implementations on target platforms.
The IP core maintains compatibility with SDA OCT 3.1.0 as defined in Document ID SDA-9100-001-08 (March 2024) and is fully compliant with the Optical Communications Terminal (OCT) Standard Version 4.0.0, Document ID SDA-9100-001-09 (August 2024). Backward compatibility with SDA OCT 3.0 is preserved to support continuity for existing designs.
The SDA OCT IP Core uses a generic and portable architecture. It is deployable on AMD and Altera FPGA platforms, with support for additional FPGA vendors available upon request to provide long-term hardware flexibility.
