Synopsys and Samsung Foundry collaborate on AI and multi-die designs for advanced process nodes

Synopsys and Samsung Foundry have continued their collaboration to support advanced edge AI, high-performance computing (HPC), and AI applications. The partnership has resulted in a successful customer tape-out of an HBM3 design on Samsung’s SF2 process using Synopsys’ 3DIC Compiler and Samsung’s I-CubeS 2.5D packaging technology, reducing HBM routing time to 4 hours and improving worst-case eye opening by 6%. The 3DIC Compiler, certified for Samsung’s X-Cube technology, supports 3D floorplanning, bump and Through-silicon via (TSV) planning, and early thermal analysis.
Synopsys has certified AI-driven digital and analog flows for Samsung’s SF2P process, incorporating hypercells for improved power, performance, and area (PPA). These flows, part of the Synopsys.ai full-stack EDA suite, enable faster development of system-on-chips (SoCs). A new schematic migration flow, using Synopsys ASO.ai, facilitates the transition of Samsung SF4 analog IPs to the SF2 process. The companies have also collaborated on design technology co-optimization (DTCO) to enhance PPA on SF2 and SF2P processes.
Synopsys provides a portfolio of IP optimized for Samsung’s process nodes, including SF2P, SF4X, SF5A, 8LPU, and 14LPP/U. This includes interface IP such as 224G, UCIe, PCIe 7.0, MIPI, LPDDR6X, and USB4, as well as foundation IP like embedded memories, logic libraries, GPIOs, PVT sensors, security IP, and Silicon Lifecycle Management (SLM) IP. These IPs support applications in HPC, consumer electronics, mobile devices, IoT, and automotive markets, aiming to reduce integration risks and accelerate time-to-market for customers.