Alphawave Semi has announced the delivery of its foundational AI platform IP. This platform, featuring ready-to-integrate subsystem IP for 64G UCIe, 224G SerDes, 800G/1.6T UALink, and UEC, along with reference chiplet architecture designs, is set to underpin future AI deployments.
New architectures and fabrics achieving high density and performance are being realized through the highest speed SerDes on advanced process nodes. Efficient die-to-die technologies, such as UCIe, deliver chip-to-chip connectivity not only on the same package but also for heterogeneous integration across the entire data center.
These hyper-optimized scale-up networks will link up to 1,000 GPUs to act like a single giant GPU. Multiple scale-up networks will then be connected and orchestrated over a dedicated scale-out network channel for low latency, low power, and low collisions.
“Through our unique DSP-based SerDes, manufactured using TSMC’s most advanced process nodes, our AI platform can deliver the performance required at the low-power levels needed via passive copper and low-power optical connectivity. This includes bringing optics to the XPUs and leveraging the low power, high-efficiency benefits of UCIe die-to-die connectivity (below 1pJ/bit) while capturing the long reaches of optics,” said Mohit Gupta, Senior VP & GM, Custom Silicon & IP, Alphawave Semi. “Our portfolio of silicon IP subsystems are set to be the building blocks of the custom silicon and chiplets that make up AI platforms,” continued Mohit Gupta.
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