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VLSI

Omni Design’s new ULP PVT monitor VLSI IP for 3nm semiconductor chips eliminate guardbands

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Ultra-low power VLSI IP expert Omni Design has unveiled the ODT-PVT-ULP-001C-3, a new  process, voltage, and temperature (PVT) monitor tailored for 3nm CMOS technology. Operating on a single 0.75V core-voltage supply, this ultra-low power IP simplifies integration while delivering unmatched precision for next-generation semiconductor chips, from data centers to autonomous systems.

Designed to function flawlessly across a temperature range of -40°C to 150°C, the ODT-PVT-ULP-001C-3 achieves ±4°C temperature accuracy without calibration and ±1°C after a single room-temperature trim. Its voltage monitor supports four differential or single-ended inputs, handling voltages up to ±0.75V, while a one-shot mode enables on-demand measurements, minimizing power use by entering a low-power standby state when idle. The process monitor provides clear digital insights into core and I/O PMOS and NMOS transistor variations, aiding design optimization.

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As 3nm designs push thermal and power boundaries, Omni’s PVT monitor eliminates the need for complex guard bands, enabling dynamic voltage and frequency scaling (DVFS) to maximize performance. It supports real-time monitoring to mitigate silicon aging, enhance reliability, and counter side-channel security risks. The solution also collects thermal data to inform future designs, speeding time-to-market for advanced chips.

“Omni Design’s PVT monitor simplifies deployment in 3nm designs with a single core-voltage rail, unlocking significant power savings,” said Dr. Kush Gulati, President and CEO of Omni Design Technologies. “Saving just 1% power in data centers through our solution can translate to over $3M in annual operating cost reductions.”

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Part of the OmniTRUST family, this compact, low-power monitor is customizable across multiple semiconductor foundries and process nodes. By enabling adaptive power management, thermal regulation, and predictive reliability, the ODT-PVT-ULP-001C-3 can help in designing AI and high performance chips lasting longer, work at optimal performance and also secure from side-channel security attacks.

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Srinivasa Reddy N

Editor, Electronics Engineering Herald


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